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PDF H5PS1G63JFR-xxC Data sheet ( Hoja de datos )
| Número de pieza | H5PS1G63JFR-xxC | |
| Descripción | 1Gb DDR2 SDRAM | |
| Fabricantes | hynix | |
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H5PS1G63JFR Series
1Gb DDR2 SDRAM
H5PS1G63JFR-xxC
H5PS1G63JFR-xxI
H5PS1G63JFR-xxL
H5PS1G63JFR-xxJ
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.7 / Nov. 2011
1
Free Datasheet http://www.datasheetlist.com/
1 page  
Release
H5PS1G63JFR Series
Ordering Information
Part No.
H5PS1G63JFR-xx*C
H5PS1G63JFR-xx*I
H5PS1G63JFR-xx*L
Configura-
tion
64Mx16
Power Consumption
Normal Consumption
Normal Consumption
Low Power Consumption
(IDD6 Only)
Operation Temp
Commercial
Industrial
Commercial
Package
84 Ball
fBGA
H5PS1G63JFR-xx*J
Low Power Consumption
(IDD6 Only)
Industrial
Note:
-XX* is the speed bin, refer to the Operating Frequency table for complete part number.
-xxP and xxQ are the low current bin, refer to the IDD specification table.
- Hynix Halogen-free products are compliant to RoHS.
Hynix supports Lead & Halogen free parts for each speed grade with same specification, except Lead free materials.
We'll add "R" character after "F" for Lead & Halogen free products
Operating Frequency
Grade
E3
C4
Y5
S6
S5
G7
Note:
tCK(ns)
5
3.75
3
2.5
2.5
1.875
CL
3
4
5
6
5
7
tRCD
3
4
5
6
5
7
tRP
3
4
5
6
5
7
Unit
Clk
Clk
Clk
Clk
Clk
Clk
-G7 is a special speed product used in electronic engineering for high speed storage of the working data of a consumer
digital electronic device.
- x16 product only
Rev. 1.7 / Nov 2011
5
Free Datasheet http://www.datasheetlist.com/
5 Page 
Release
H5PS1G63JFR Series
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
Symbol
VIH(dc)
VIL(dc)
Parameter
dc input logic HIGH
dc input logic LOW
3.2.2 Input AC Logic Level
Min.
VREF + 0.125
- 0.3
Max.
VDDQ + 0.3
VREF - 0.125
Units
V
V
Symbol
VIH (ac)
VIL (ac)
Parameter
ac input logic HIGH
ac input logic LOW
DDR2 400,533
DDR2 667,800
Min.
Max.
Min.
Max.
VREF + 0.250 VDDQ+Vpeak VREF + 0.200 VDDQ+Vpeak
VSSQ-Vpeak VREF - 0.250 VSSQ-Vpeak VREF - 0.200
Units
V
V
Symbol
VIH (ac)
VIL (ac)
Parameter
ac input logic HIGH
ac input logic LOW
DDR2 1066
Min.
VREF + 0.200
Max.
VDDQ+Vpeak
VSSQ-Vpeak
VREF - 0.200
3.2.3 AC Input Test Conditions
Units
V
V
Notes
Notes
Notes
Symbol
VREF
VSWING(MAX)
SLEW
Condition
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
Value
0.5 * VDDQ
1.0
1.0
Units
V
V
V/ns
Notes
1
1
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
VSWING(MAX)
delta TF
delta TR
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
Falling Slew = VREF - VIL(ac) max
delta TF
Rising Slew = VIH(ac) min - VREF
delta TR
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising
edges and the range from VREF to VIL(ac) max for falling edges as shown in the figure below.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
Rev. 1.7 / Nov. 2011
11
Free Datasheet http://www.datasheetlist.com/
11 Page | ||
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