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PDF HEF4071B Data sheet ( Hoja de datos )
| Número de pieza | HEF4071B | |
| Descripción | Quadruple 2-input OR gate | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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HEF4071B
Quad 2-input OR gate
Rev. 8 — 16 December 2015
Product data sheet
1. General description
The HEF4071B is a quad 2-input OR gate. The outputs are fully buffered for highest noise
immunity and pattern insensitivity to output impedance variations.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
Specified from 40 C to +85 C and 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +125 C.
Type number
Package
Name
Description
HEF4071BT
SO14
plastic small outline package; 14 leads; body width 3.9 mm
Version
SOT108-1
4. Functional diagram
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Fig 1. Functional diagram
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Fig 2. Logic diagram (one gate)
1 page  
NXP Semiconductors
HEF4071B
Quad 2-input OR gate
10. Dynamic characteristics
Table 7. Dynamic characteristics
Tamb = 25 C; waveforms see Figure 4; test circuit see Figure 5; unless otherwise specified. [1]
Symbol Parameter
Conditions VDD
Extrapolation formula Min Typ Max Unit
tPHL HIGH to LOW
nA or nB to nY 5 V
28 ns + (0.55 ns/pF)CL - 55 115 ns
propagation delay
10 V 15 ns + (0.23 ns/pF)CL - 25 50 ns
15 V 12 ns + (0.16 ns/pF)CL - 20 35 ns
tPLH LOW to HIGH
nA or nB to nY 5 V
18 ns + (0.55 ns/pF)CL - 45 90 ns
propagation delay
10 V
9 ns + (0.23 ns/pF)CL - 20 45 ns
15 V
7 ns + (0.16 ns/pF)CL - 15 30 ns
tt transition time
5 V [2] 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V
9 ns + (0.42 ns/pF)CL - 30 60 ns
15 V
6 ns + (0.28 ns/pF)CL - 20 40 ns
[1] The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
[2] tt is the same as tTHL and tTLH.
Table 8. Dynamic power dissipation
VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD Typical formula
where:
PD dynamic power dissipation 5 V PD = 1150 fi + (fo CL) VDD2 (W) fi = input frequency in MHz;
10 V
15 V
PD = 4800 fi + (fo CL) VDD2 (W)
PD = 19700 fi + (fo CL) VDD2 (W)
fo = output frequency in MHz;
CL = output load capacitance in pF;
(fo CL) = sum of the outputs;
VDD = supply voltage in V.
HEF4071B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 16 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 11
5 Page 
NXP Semiconductors
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 1
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Functional description . . . . . . . . . . . . . . . . . . . 2
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
8 Recommended operating conditions. . . . . . . . 3
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 8
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 9
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 9
15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
16 Contact information. . . . . . . . . . . . . . . . . . . . . 10
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
HEF4071B
Quad 2-input OR gate
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 16 December 2015
Document identifier: HEF4071B
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet HEF4071B.PDF ] | |
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