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PDF HEF4051B Data sheet ( Hoja de datos )
| Número de pieza | HEF4051B | |
| Descripción | 8-channel analogue multiplexer/demultiplexer | |
| Fabricantes | NXP Semiconductors | |
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HEF4051B
8-channel analog multiplexer/demultiplexer
Rev. 11 — 11 September 2014
Product data sheet
1. General description
The HEF4051B is an 8-channel analog multiplexer/demultiplexer with three address
inputs (S1 to S3), an active LOW enable input (E), eight independent inputs/outputs
(Y0 to Y7) and a common input/output (Z). The device contains eight bidirectional analog
switches, each with one side connected to an independent input/output (Y0 to Y7) and the
other side connected to a common input/output (Z). With E LOW, one of the eight
switches is selected (low-impedance ON-state) by S1 to S3. With E HIGH, all switches
are in the high-impedance OFF-state, independent of S1 to S3. If break before make is
needed, then it is necessary to use the enable input.
VDD and VSS are the supply voltage connections for the digital control inputs (S1 to S3,
and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (Y0 to Y7, and Z)
can swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not
exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically
ground). VEE and VSS are the supply voltage connections for the switches.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C and 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
1 page  
NXP Semiconductors
HEF4051B
8-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
HEF4051B
Y4 1
Y6 2
16 VDD
15 Y2
Z3
14 Y1
Y7 4
13 Y0
Y5 5
12 Y3
E6
11 S1
VEE 7
VSS 8
10 S2
9 S3
001aak508
Fig 6. Pin configuration SOT38-4 and SOT109-1
HEF4051B
Y4 1
Y6 2
Z3
Y7 4
Y5 5
E6
VEE 7
VSS 8
16 VDD
15 Y2
14 Y1
13 Y0
12 Y3
11 S1
10 S2
9 S3
001aac282
Fig 7. Pin configuration SOT338-1 and SOT403-1
6.2 Pin description
Table 2. Pin description
Symbol
Pin
E6
VEE
VSS
S1, S2, S3
7
8
11, 10, 9
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4
Z3
VDD 16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
common output or input
supply voltage
HEF4051B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
HEF4051B
8-channel analog multiplexer/demultiplexer
Table 8. Dynamic characteristics …continued
Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 16.
Symbol Parameter
Conditions
tPZL OFF-state to LOW
propagation delay
E to Yn, Z; see Figure 15
11.1 Waveforms and test circuit
VDD
5V
10 V
15 V
Typ Max Unit
140 280 ns
55 110 ns
40 80 ns
Yn or Z
input
Z or Yn
output
VDD
VEE
VO
VEE
tPLH
VM
VM
tPHL
001aak509
Measurement points are given in Table 9.
Fig 13. Yn, Z to Z, Yn propagation delays
VDD
Sn input
VSS
VO
Yn or Z
output
VEE
VM
tPLH
switch OFF
tPHL
10 %
switch ON
90 %
switch OFF
001aak510
Measurement points are given in Table 9.
Fig 14. Sn to Yn, Z propagation delays
E input
VDD
VSS
Yn or Z output
LOW-to-OFF
OFF-to-LOW
VO
VEE
Yn or Z output
HIGH-to-OFF
OFF-to-HIGH
VO
VEE
Measurement points are given in Table 9.
Fig 15. Enable and disable times
VM
tPLZ
tPZL
90 %
tPHZ
10 %
90 %
tPZH
switch ON
switch OFF
10 %
switch ON
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Table 9. Measurement points
Supply voltage
VDD
5 V to 15 V
Input
VM
0.5VDD
Output
VM
0.5VDD
HEF4051B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 11 — 11 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 23
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