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PDF OP07 Data sheet ( Hoja de datos )
| Número de pieza | OP07 | |
| Descripción | Ultralow Offset Voltage Operational Amplifiers | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Low VOS: 75 μV maximum
Low VOS drift: 1.3 μV/°C maximum
Ultrastable vs. time: 1.5 μV per month maximum
Low noise: 0.6 μV p-p maximum
Wide input voltage range: ±14 V typical
Wide supply voltage range: ±3 V to ±18 V
125°C temperature-tested dice
APPLICATIONS
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls
Thermocouples
Resistor thermal detectors (RTDs)
Strain bridges
Shunt current measurements
Precision filters
GENERAL DESCRIPTION
The OP07 has very low input offset voltage (75 μV maximum for
OP07E) that is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external
nulling. The OP07 also features low input bias current (±4 nA for
the OP07E) and high open-loop gain (200 V/mV for the OP07E).
The low offset and high open-loop gain make the OP07
particularly useful for high gain instrumentation applications.
Ultralow Offset Voltage
Operational Amplifier
OP07
PIN CONFIGURATION
VOS TRIM 1
–IN 2
+IN 3
V– 4
OP07
8 VOS TRIM
7 V+
6 OUT
5 NC
NC = NO CONNECT
Figure 1.
The wide input voltage range of ±13 V minimum combined
with a high CMRR of 106 dB (OP07E) and high input
impedance provide high accuracy in the noninverting circuit
configuration. Excellent linearity and gain accuracy can be
maintained even at high closed-loop gains. Stability of offsets
and gain with time or variations in temperature is excellent. The
accuracy and stability of the OP07, even at high gain, combined
with the freedom from external nulling have made the OP07 an
industry standard for instrumentation applications.
The OP07 is available in two standard performance grades. The
OP07E is specified for operation over the 0°C to 70°C range,
and the OP07C is specified over the −40°C to +85°C
temperature range.
The OP07 is available in epoxy 8-lead PDIP and 8-lead narrow
SOIC packages. For CERDIP and TO-99 packages and standard
microcircuit drawing (SMD) versions, see the OP77.
V+
7
R2A1
R1A
(OPTIONAL
1 NULL) 8
R2B1
R1B
C1
NONINVERTING
INPUT 3
INVERTING
INPUT 2
Q5
R3
Q21
R4 Q22
Q7
Q3 Q6
Q1
Q23
Q24
Q8
Q4
Q2
Q9
Q11
Q10
Q12
Q27 C3
R5
Q26
Q25
C2
Q14
Q17
4
V–
Q13
1R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY FOR MINIMUM INPUT OFFSET VOLTAGE.
Figure 2. Simplified Schematic
R7
Q19
Q16
Q15
Q18
R9
OUT
6
R10
Q20
R6 R8
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002-2011 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.Datasheet-PDF.com/
1 page  
Data Sheet
OP07
Parameter
OUTPUT CHARACTERISTICS
TA = 25°C
Output Voltage Swing
−40°C ≤ TA ≤ +85°C
Output Voltage Swing
DYNAMIC PERFORMANCE
TA = 25°C
Slew Rate
Closed-Loop Bandwidth
Open-Loop Output Resistance
Power Consumption
Offset Adjustment Range
Symbol Conditions
VO RL ≥ 10 kΩ
RL ≥ 2 kΩ
RL ≥ 1 kΩ
VO RL ≥ 2 kΩ
SR RL ≥ 2 kΩ3
BW AVOL = 15
RO VO = 0, IO = 0
Pd VS = ±15 V, No load
VS = ±3 V, No load
RP = 20 kΩ
Min Typ Max Unit
±12.0
±11.5
±13.0
±12.8
±12.0
±12 ±12.6
V
V
V
V
0.1 0.3
V/μs
0.4 0.6
MHz
60 Ω
80 150 mW
4 8 mW
±4 mV
1 Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
2 Long-term input offset voltage stability refers to the averaged trend time of VOS vs. the time over extended periods after the first 30 days of operation. Excluding the
initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 μV. Refer to the Typical Performance Characteristics section. Parameter is
sample tested.
3 Sample tested.
4 Guaranteed by design.
5 Guaranteed but not tested.
Rev. G | Page 5 of 16
Free Datasheet http://www.Datasheet-PDF.com/
5 Page 
Data Sheet
TYPICAL APPLICATIONS
R1
EIN
V+
7
2–
OP07C
A1
3
+
4
RF
SUM MODE
BIAS
V+
R3
3kΩ
2–
7
R5
6 10kΩ
AD7115 OR
AD8510
3
+
R2
100kΩ
4
V–
6
V–
EO
=
–EIN
RF
R1
–IB
RF
Figure 26. Typical Offset Voltage Test Circuit
EO
R4
10kΩ
R1
10kΩ
E1
+15V
R2
10kΩ
E2
7
2–
R3
10kΩ
E3
6
OP07C
EO
3
+
R5
2.5kΩ
4
–15V
Figure 27. Typical Low Frequency Noise Circuit
–
INPUT
+
20kΩ
1
2–
8
OP07
7
3
+
4
6
V+
OUT
V–
Figure 28. Optional Offset Nulling Circuit
OP07
R3
10kΩ
R4
10kΩ
R5
10kΩ
EIN
±10V
R1
10kΩ
V+
7
2–
FD333
D1
OP07
6
3
+
4
FD333
D2
R2
V– 10kΩ
V+
7
2–
OP07
3
+
4
6
EO
0V TO +10V
V–
R1
R3
=
R2
R4
Figure 29. Absolute Value Circuit
R1
EIN
V+
7
2–
OP07C
A1
3
+
4
RF
SUM MODE
BIAS
V+
R3
3kΩ
2–
7
OP07C
R1
6 10kΩ 3
+
A2
R2
100kΩ
4
V–
6
V–
EO
=
–EIN
RF
R1
+
IB
RF
NOTES
1. PINOUT SHOWN FOR P PACKAGE
Figure 30. High Speed, Low VOS Composite Amplifier
EO
R4
10kΩ
R1
10kΩ
E1
R2
10kΩ
E2
R3
10kΩ
E3
R5
2.5kΩ
+15V
7
2–
OP07
3
+
4
6
EO
–15V
NOTES
1. PINOUT SHOWN FOR P PACKAGE
Figure 31. Adjustment-Free Precision Summing Amplifier
Rev. G | Page 11 of 16
Free Datasheet http://www.Datasheet-PDF.com/
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet OP07.PDF ] | |
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