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PDF K9G8G08B0A Data sheet ( Hoja de datos )
| Número de pieza | K9G8G08B0A | |
| Descripción | FLASH MEMORY | |
| Fabricantes | Samsung | |
| Logotipo |  |
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K9LAG08U1A
K9G8G08U0A K9G8G08B0A
Preliminary
FLASH MEMORY
K9XXG08XXA
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
Free Datasheet http://www.datasheet4u.net/
1 page  
K9LAG08U1A
K9G8G08U0A K9G8G08B0A
PIN CONFIGURATION (ULGA)
K9G8G08U0A-ICB0/IIB0
A B C DE FG HJ K L M N
NC NC
NC
NC NC NC
7
NC /RE
NC
NC NC
NC
NC
6
Vcc NC Vss IO7 IO5
Vcc
5
4
/CE NC R/B
NC IO6
IO4
NC
3 CLE NC /WE IO0 IO2 Vss NC
2
Vss NC /WP IO1 IO3
Vss
1
NC ALE NC
NC NC
NC NC
NC NC NC
NC NC NC
Preliminary
FLASH MEMORY
PACKAGE DIMENSIONS
52-ULGA (measured in millimeters)
Top View
12.00±0.10
#A1
(Datum A)
(Datum B)
A
B
C
D
E
F
G
H
J
K
L
M
N
Bottom View
2.00
7
12.00±0.10
1.00 10.00 1.00
6 54 3 2
1
1.00
1.00
A
B
0.10 C
12-∅1.00±0.05
∅0.1 M C AB
Side View
17.00±0.10
41-∅0.70±0.05
∅0.1 M C AB
5
Free Datasheet http://www.datasheet4u.net/
5 Page 
K9LAG08U1A
K9G8G08U0A K9G8G08B0A
Preliminary
FLASH MEMORY
VALID BLOCK
Parameter
K9G8G08X0A
K9LAG08U1A
Symbol
NVB
NVB
Min
3,996
7,992
Typ.
-
Max
4,096
8,192
Unit
Blocks
Blocks
NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or pro-
gram factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
3. The number of valid blocks is on the basis of single plane operations, and this may be decreased with two plane operations.
* : Each K9G8G08U0A chip in the K9LAG08U1A has Maximum 100 invalid blocks.
AC TEST CONDITION
(K9XXG08XXM-XCB0 :TA=0 to 70°C, K9XXG08XXM-XIB0:TA=-40 to 85°C,
K9G8G08B0A: Vcc=2.5V~2.9V, K9XXG08UXM: Vcc=2.7V~3.6V unless otherwise)
Parameter
K9G8G08B0A
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL=30pF
K9XXG08UXM
0V to Vcc
5ns
Vcc/2
1 TTL GATE and CL=50pF
CAPACITANCE(TA=25°C, VCC=2.7V/3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
CIN
Test Condition
VIL=0V
VIN=0V
NOTE : Capacitance is periodically sampled and not 100% tested.
Min
-
-
Max
10
10
Unit
pF
pF
MODE SELECTION
CLE
ALE
CE
WE
RE
HL L
H
LHL
H
HL L
H
LHL
H
LLL
H
L L LH
XXXXH
XXXXX
XXXXX
X X(1) X X X
XXHXX
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
WP
X
X
H
H
H
X
X
H
H
L
0V/VCC(2)
Mode
Read Mode
Command Input
Address Input(5clock)
Write Mode
Command Input
Address Input(5clock)
Data Input
Data Output
During Read(Busy)
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
11
Free Datasheet http://www.datasheet4u.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet K9G8G08B0A.PDF ] | |
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