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PDF HG74ALVC16835C Data sheet ( Hoja de datos )
| Número de pieza | HG74ALVC16835C | |
| Descripción | 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS | |
| Fabricantes | Hynix Semiconductor | |
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18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
HG74ALVC16835C
Jan 1999
Features
l Ideal for Use in PC100 Registered DIMM
l 0.5µm CMOS Technology
l 2.3 ~ 3.6 VCC Operation
l Balanced Output Drive(±24mA)
l Package Options Include Plastic Thin
Shrink Small-Outline Packages, Shrink
Small-Outline Packages
(TSSOP 56 Pins, SSOP 56 Pins, TVSOP56 Pins)
Pin Configuration
NC
NC
Y1
GND
Y2
Y3
Vcc
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
Vcc
Y16
Y17
GND
Y18
OE
LE
(TOP VIEW)
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
GND
NC
A1
GND
A2
A3
Vcc
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
Vcc
A16
A17
GND
A18
CLK
GND
General Description
The HG74ALVC16835C is an 18-bit universal bus
driver designed for 2.3V to 3.6 V VCC Operation.
The Output-Enable(OE) controls data flow from A to Y.
The device operates in transparent mode when the
latch-enable(LE) input is high. When LE is low, the A
data is latched if the clock input is held at a high or low
logic level.
If LE is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK.
When OE is high, the Outputs are in the high
impedance state. OE should be tied to VCC through a
pull up resistor to ensure the high impedance state
during power up or power down.
The HG74ALVC16835C is characterized for operation
from -40°C to 85°C.
Function Table
INPUTS
OUTPUT
OE LE CLK A
Y
H X XX
Z
L H XL
L
L H XH
H
L L ↑L
L
L L ↑H
H
L L L or H X
YO=
=Output level before the indicated steady-state input
conditions were established, provided that CLK is high
before LE goes low.
NC- No ineternal connection
1
Copyright ©1999, Hyundai Electronics Industries Co., Ltd.
ELECTRONICS
1 page  
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
Voltage Waveforms
HG74ALVC16835C
Jan 1999
Timing
Input
Data
Input
VCC /2
tsu th
VCC /2
VCC
0V
VCC /2
VCC
0V
Figure 2. Set up and Hold Times
Input
tw
VCC /2
VCC /2
VCC
0V
Figure 3. Pulse Duration
Input
tPLH
Output
VCC /2
VCC /2
VCC
0V
tPHL
VCC/2
VCC /2
VOH
VOL
Figure 4. Propagation Delay times
Output Control
(Low-level enabling)
Output Waveform 1
S1 at 2 x VCC
(See Note 1 )
Output Waveform 2
S1 at GND
(See Note 1 )
tPZL
tPZH
VCC /2
VCC /2
VCC /2
VCC /2
tPLZ
VOL + 0.15V
tPHZ
VOH - 0.15V
Figure 5. Enable and Disable Times
VCC
0V
VCC
VOL
VOH
0V
Note 1 )Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control
Note 2) All input pulses are supplied by generators having the following characteristics:
PRR ⊆ 10Mhz, Zo = 50Ω , tr ⊆ 2ns, tf ⊆ 2ns.
Note 3) The output are measured one at a time with one transition per measurement.
Note 4) tPLZ and tPHZ are the same as tdis.
Note 5) tPZL and tPZH are the same as ten .
Note 6) tPLH and tPHL are the same as tpd.
5
Copyright ©1999, Hyundai Electronics Industries Co., Ltd.
ELECTRONICS
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet HG74ALVC16835C.PDF ] | |
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