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HG74ALVC162835C fiches techniques PDF

Hynix Semiconductor - 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

Numéro de référence HG74ALVC162835C
Description 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
Fabricant Hynix Semiconductor 
Logo Hynix Semiconductor 





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HG74ALVC162835C fiche technique
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
HG74ALVC162835C
Jan. 1999
Features
General Description
l Ideal for Use in PC100 Registered DIMM
l 0.5µm CMOS Technology
l 2.3 ~ 3.6 VCC Operation
l Output Port Has 26-Series Damping
Resistor, No External Resistors are Required
l Package Options Include Plastic Thin Shrink
Small-Outline Packages, Shrink Small-Outline
Packages , Thin Very Small Outline Packages
(TSSOP 56 Pins, SSOP 56 Pins , TVSOP 56 Pins)
Pin Configuration
The HG74ALVC162835C is an 18-bit universal bus
driver designed for 2.3V to 3.6 V VCC Operation.
The Output Enable(OE) controls data flow from A to Y.
The device operates in transparent mode when the
latch-enable(LE) input is high. When LE is low, the A
data is latched if the clock input is held at a high or low
logic level. If LE is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLK.
When OE is high, the Outputs are in the high
impedance state. OE should be tied to VCC through a
pull up resistor to ensure the high impedance state
during power up or power down.
NC
NC
Y1
GND
Y2
Y3
Vcc
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
Vcc
Y16
Y17
GND
Y18
OE
LE
(TOP VIEW)
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 43
15 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
GND
NC
A1
GND
A2
A3
Vcc
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
Vcc
A16
A17
GND
A18
CLK
GND
The equivalent 26-series resistors are included in
the output to reduce overshoot and undershoot.
The HG74ALVC162835C is characterized for operation
from -40°C to 85°C.
Function Table
INPUTS
OUTPUT
OE LE CLK A
Y
H X XX
Z
L H XL
L
L H XH
H
L L L
L
L L H
H
L L L or H X
YO=
=Output level before the indicated steady-state input
conditions were established, provided that CLK is high
before LE goes low.
NC- No ineternal connection
Copyright ©1999, Hyundai Electronics Industries Co., Ltd.
ELECTRONICS

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