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PDF W49F002A Data sheet ( Hoja de datos )

Número de pieza W49F002A
Descripción 256K x 8 CMOS Flash Memory
Fabricantes Winbond 
Logotipo Winbond Logotipo



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No Preview Available ! W49F002A Hoja de datos, Descripción, Manual

Preliminary W49F002A
256K × 8 CMOS FLASH MEMORY
GENERAL DESCRIPTION
The W49F002A is a 2-megabit, 5-volt only CMOS flash memory organized as 256K × 8 bits. The
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is
not required. The unique cell architecture of the W49F002A results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory products).
The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt operations:
5-volt Read
5-volt Erase
5-volt Program
Fast program operation:
Byte-by-byte programming: 35 µS (typ.)
Fast erase operation: 100 mS (typ.)
Fast read access time: 120 nS
Ten-year data retention
Hardware data protection
One 16K byte Boot Block with Lockout
protection
Typical page write (erase/program) cycles:
10 100
Two 8K byte parameter blocks
Two main memory blocks (96K, 128K) Bytes
Low power consumption
Active current: 25 mA (typ.)
Standby current: 20 µA (typ.)
Automatic program and erase timing with
internal VPP generation
End of program or erase detection
Toggle bit
Data polling
Latched address and data
TTL compatible I/O
JEDEC standard byte-wide pinouts
Available packages: 32-pin DIP and PLCC
Publication Release Date: September 12, 2001
- 1 - Revision A1
Free Datasheet http://www.datasheet4u

1 page




W49F002A pdf
Preliminary W49F002A
Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read
mode.
Read Command
The device will automatically power-up in the read state. In this case, a command sequence is not
required to read data. Standard microprocessor read cycles will retrieve array data. This default value
ensures that no spurious alteration of the memory content occurs during the power transition.
The device will automatically returns to read state after completing an Embedded Program or
Embedded Erase algorithm.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.
Auto-select Command
Flash memories are intended for use in applications where the local CPU can alter memory contents.
As such, manufacture and device codes must be accessible while the device resides in the target
system. PROM programmers typically access the signature codes by raising A9 to a high voltage.
However, multiplexing high voltage onto the address lines is not generally a desirable system design
practice.
The device contains an auto-select command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the auto-select command sequence into the
command register. Following the command write, a read cycle from address XX00H retrieves the
manufacture code of DAh. A read cycle from address XX01H returns the device code (W49F002A =
0Bh).
Byte Program Command
The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The
program command sequence is initiated by writing two "unlock" write cycles, followed by the program
set-up command. The program address and data are written next, which in turn initiate the Embedded
program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later
and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of
#CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm.
Upon executing the algorithm, the system is not required to provide further controls or timings. The
device will automatically provide adequate internally generated program pulses and verify the
programmed cell margin.
The automatic programming operation is completed when the data on DQ7 (also used as Data Polling)
is equivalent to the data written to this bit at which time the device returns to the read mode and
addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that
a valid address to the device be supplied by the system at this particular instance of time for Data
Polling operations. Data Polling must be performed at the memory location which is being
programmed.
Publication Release Date: September 12, 2001
- 5 - Revision A1
Free Datasheet http://www.datasheet4u

5 Page





W49F002A arduino
Preliminary W49F002A
Embedded Algorithms, continued
Start
Read Byte
(DQ0-DQ7)
Address = VA
VA = Byte address for programming
= Any of the sector addresses within
the sector being erased during sector
erase operation
= Valid address equals any sector group
address during chip erase
No
DQ7 = Data
?
Yes
Pass
#Data Polling Algorithm
Start
Read Byte
(DQ0-DQ7)
Address = Don' t Care
No
DQ6 = Toggle
?
Yes
Fail
Toggle Bit Algorithm
- 11 -
Publication Release Date: September 12, 2001
Revision A1
Free Datasheet http://www.datasheet4

11 Page







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