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PDF WM8259 Data sheet ( Hoja de datos )

Número de pieza WM8259
Descripción Single Channel 16-Bit CIS/CCD AFE
Fabricantes Wolfson 
Logotipo Wolfson Logotipo



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WM8259
Single Channel 16-bit CIS/CCD AFE with 4-bit Wide Output
DESCRIPTION
The WM8259 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 3MSPS.
The device has two selectable video input pins and one
complete analogue signal processing channel containing
Reset Level Clamping, Correlated Double Sampling,
Programmable Gain and Offset adjust functions. Internal
multiplexers allow fast switching of offset and gain for line-
by-line colour processing. The output from this channel is
time multiplexed into a high-speed 16-bit Analogue to Digital
Converter. The digital output data is available in 4-bit wide
multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
The device uses an analogue supply voltage of 3.3V and a
digital interface supply of between 2.5V and 3.3V. The
WM8259 typically only consumes 132mW when operating
from a single 3.3V supply.
BLOCK DIAGRAM
FEATURES
16-bit ADC
3MSPS conversion rate
Low power - 132mW typical
3.3V single supply or 3.3V/2.5V dual supply operation
Single channel operation, selectable inputs
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
4-bit wide multiplexed data output format
Internally generated voltage references
20-lead SSOP package
Serial control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/
Production Data, April 2007, Rev 4.2
Copyright ©2007 Wolfson Microelectronics plc

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WM8259 pdf
WM8259
Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
MIN MAX
Analogue supply voltage: AVDD
GND - 0.3V
GND + 4.2V
Digital core supply voltage: DVDD1
GND - 0.3V
GND + 4.2V
Digital IO supply voltage: DVDD2
GND - 0.3V
GND + 4.2V
Digital ground: DGND
GND - 0.3V
GND + 0.3V
Analogue grounds AGND
GND - 0.3V
GND + 0.3V
Digital inputs, digital outputs and digital I/O pins
GND - 0.3V
DVDD + 0.3V
Analogue inputs (VINP1, VINP2)
GND - 0.3V
AVDD + 0.3V
Other pins
GND - 0.3V
AVDD + 0.3V
Operating temperature range: TA
0°C +70°C
Notes:
1. GND denotes the voltage of any ground pin.
2. AGND and DGND pins are intended to be operated at the same potential. Differential voltages between these pins
will degrade performance.
3. AVDD and DVDD1 pins are intended to be operated at the same potential. Differential voltages between these pins
will degrade performance.
RECOMMENDED OPERATING CONDITIONS
CONDITION
Operating temperature range
Analogue supply voltage
Digital Core supply voltage
Digital I/O supply voltage
SYMBOL
MIN
TYP
MAX
UNITS
TA 0
70 °C
AVDD
2.97
3.3
3.63
V
DVDD1
2.97
3.3
3.63
DVDD2
2.5
3.3 3.63
V
V
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PD Rev 4.2 April 2007
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WM8259 arduino
WM8259
Production Data
Figure 4 Reset Level Clamping and CDS Circuitry
Reset Level Clamping is controlled by register bit RLCINT. Figure 5 illustrates the effect of the
RLCINT bit for a typical CCD waveform, with CL applied during the reset period.
The RLCINT register bit is sampled on the positive edge of MCLK that occurs during each VSMP
pulse. The sampled level, high (or low) controls the presence (or absence) of the internal CL pulse on
the next reset level. The position of CL can be adjusted by using control bits CDSREF[1:0] (Figure 6).
Figure 5 Relationship of RLCINT, MCLK and VSMP to Internal Clamp Pulse, CL
The VRLC/VBIAS pin can be driven internally by a 4-bit DAC (RLCDAC) by writing to control bits
RLCV[3:0]. The RLCDAC range and step size may be increased by writing to control bit
RLCDACRNG. Alternatively, the VRLC/VBIAS pin can be driven externally by writing to control bit
VRLCEXT to disable the RLCDAC and then applying a d.c. voltage to the pin.
CDS/NON-CDS PROCESSING
For CCD type input signals, the signal may be processed using CDS, which will remove pixel-by-pixel
common mode noise. For CDS operation, the video level is processed with respect to the video reset
level, regardless of whether RLC has been performed. To sample using CDS, control bit CDS must
be set to 1 (default), this controls switch 2 (Figure 4) and causes the signal reference to come from
the video reset level. The time at which the reset level is sampled, by clock Rs/CL, is adjustable by
programming control bits CDSREF[1:0], as shown in Figure 6.
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PD Rev 4.2 April 2007
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