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PDF ADuM1241 Data sheet ( Hoja de datos )
| Número de pieza | ADuM1241 | |
| Descripción | (ADuM1240 - ADuM1246) Dual-Channel Digital Isolators | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Micropower, Dual-Channel Digital Isolators
ADuM1240/ADuM1241/ADuM1245/ADuM1246
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Ultralow power operation
3.3 V operation
16 µA per channel maximum quiescent current, refresh
enabled
0.3 µA per channel typical quiescent current, refresh
disabled
148 µA/Mbps per channel typical dynamic current
2.5 V operation
8 µA per channel maximum quiescent current, refresh
enabled
0.1 µA per channel typical quiescent current, refresh
disabled
116 µA/Mbps per channel typical dynamic current
Small, 20-lead SSOP package
Bidirectional communication
Up to 2 Mbps data rate (NRZ)
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/μs
Safety and Regulatory Approvals
UL 1577 component recognition program (pending)
3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 849 V peak
APPLICATIONS
General-purpose, low power, multichannel isolation
1 MHz low power SPI
4 mA to 20 mA loop process control
GENERAL DESCRIPTION
The ADuM1240/ADuM1241/ADuM1245/ADuM12461 are
micropower, dual-channel digital isolators based on the Analog
Devices, Inc., iCoupler® technology. Combining high speed CMOS
and monolithic air core transformer technologies, these isolation
components provide outstanding performance characteristics supe-
rior to alternatives, such as optocoupler devices, yet consume
extremely low power.
Packaged in a 20-lead SSOP, this series of dual, 3.75 kV rms
digital isolation devices operate with supplies as low as 2.25 V
and typically consume a minimal current of less than 6 µA per
channel at data rates below 20 kbps, a fraction of the power of
comparable isolators at comparable data rates (up to 2 Mbps).
In addition, all models provide low pulse width distortion (<8 ns)
VDD1 1
GND1 2
NIC 3
ADuM124x
20 VDD2
19 GND2
18 NIC
NIC 4
17 NIC
VIA/VOA 5
ENCODE
DECODE
16 VOA/VIA
VIB 6
EN1 7
NIC 8
NIC 9
GND1 10
ENCODE
DECODE
15 VOB
14 EN2
13 NIC
12 NIC
11 GND2
Figure 1.
and an input glitch filter for extraneous noise disturbance protec-
tion. All models operate with an independent supply voltage on
either side (between 2.25 V and 3.6 V), providing compatibility
with lower voltage systems and enabling voltage level translation
functionality across the isolation barrier. In the absence of input
power, the products default to a predetermined output logic state:
the ADuM1240 and ADuM1241 default to high output, and the
ADuM1245 and ADuM1246 default to low output.
PRODUCT HIGHLIGHTS
1. Microwatt Power. These 3.75 kV digital isolators consume
less than 15 μW per channel quiescent and 950 μW per
channel at 2 Mbps.
2. Low Supply Operation. Supports power supply voltages down
to 2.25 V.
3. iCoupler Technology. Patented Analog Devices technology
combining high speed CMOS and monolithic air core
transformer technologies.
1000
100
10
ENx = 0
1 ENx = 1
0.1
0.1
1
10
100
1000
10000
DATA RATE (kbps)
Figure 2. Typical Total Supply Current (IDD1 + IDD2) per Channel (VDDx = 3.3 V)
1 Protected by U.S. Patents 5,952,849, 6,873,065, 7,075,329, 6,262,600. Other patents pending.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
ADuM1240/ADuM1241/ADuM1245/ADuM1246
Table 6.
Parameter
DC SPECIFICATIONS
Input Threshold
Logic High
Logic Low
Output Voltages
Logic High
Logic Low
Input Current per Channel
Input Switching Thresholds
Positive Threshold Voltage
Negative Going Threshold
Input Hysteresis
Undervoltage Lockout, VDD1 or VDD2
Supply Current per Channel
Quiescent Current
Input Supply
Output Supply
Input (Refresh Off )
Output (Refresh Off )
Dynamic Supply Current
Input
Output
AC SPECIFICATIONS
Output Rise Time/Fall Time
Common-Mode Transient Immunity2
Refresh Rate
Symbol Min
Typ Max
Unit
Test Conditions/Comments
VIH
VIL
VOH
VOL
II
VT+
VT−
ΔVT
UVLO
0.7 VDDx1
VDDx1 − 0.1
VDDx1 − 0.4
−1
0.3 VDDx1
V
V
2.5
2.35
0.0
0.1
+0.01
0.1
0.4
+1
V
V
V
V
µA
1.5 V
1.0 V
0.5 V
1.5 V
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDx1
IDDI (Q)
IDDO (Q)
IDDI (Q)
IDDO (Q)
IDDI (D)
IDDO (D)
tR/tF
|CM|
fr
25
2.6 3.75
0.5 3.75
0.05
0.05
76
41
2
40
14
µA ENX low
µA ENX low
µA ENX high
µA ENX high
µA/Mbps
µA/Mbps
ns
kV/µs
kbps
10% to 90%
VIx = VDDx1, VCM = 1000 V,
transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VOUT > 0.8 VDDx. The common-mode voltage slew rates apply to both rising and
falling common-mode voltage edges.
Rev. 0 | Page 5 of 20
Free Datasheet http://www.datasheet4u.com/
5 Page 
Data Sheet
ADuM1240/ADuM1241/ADuM1245/ADuM1246
VDD1
GND1
NIC
1
2
3
20 VDD2
19 GND2
18 NIC
NIC 4
VOA
VIB
EN1
NIC
5
6
7
8
17 NIC
ADuM1241/
ADuM1246 16 VIA
TOP VIEW 15 VOB
(Not to Scale) 14 EN2
13 NIC
NIC 9
12 NIC
GND1 10
11 GND2
NIC = NOT INTERNALLY CONNECTED.
Figure 5. ADuM1241/ADuM1246 Pin Configuration
Table 19. ADuM1241/ADuM1246 Pin Function Descriptions1
Pin No. Mnemonic Description
1 VDD1 Supply Voltage for Isolator Side 1 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range of 0.01 µF to
0.1 µF between VDD1 (Pin 1) and GND1 (Pin 2).
2
GND1
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to GND1 is
recommended.
3 NIC
Not Internally Connected. Leave this pin floating.
4 NIC
Not Internally Connected. Leave this pin floating.
5 VOA
Logic Output A.
6 VIB
Logic Input B.
7 EN1
Refresh/Watchdog Enable 1. Connecting Pin 7 to GND1 enables the input/output refresh and watchdog
functionality for Side 1, supporting standard iCoupler operation. Tying Pin 7 to VDD1 disables the refresh and
watchdog functionality for lowest power operation, see the DC Correctness and Low Power Operation section for a
description of this mode. EN1 and EN2 must be set to the same logic state.
8 NIC Not Internally Connected. Leave this pin floating.
9 NIC Not Internally Connected. Leave this pin floating.
10 GND1 Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 10 are internally connected, and connecting both to GND1 is
recommended.
11 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to GND2 is
recommended.
12 NIC
Not Internally Connected. Leave this pin floating.
13 NIC
Not Internally Connected. Leave this pin floating.
14 EN2
15 VOB
Refresh/Watchdog Enable 2. Connecting Pin 14 to GND2 enables the input/output refresh and watchdog
functionality for Side 2, supporting standard iCoupler operation. Tying Pin 14 to VDD2 disables the refresh and
watchdog functionality for lowest power operation, see the DC Correctness and Low Power Operation section for a
description of this mode. EN1 and EN2 must be set to the same logic state.
Logic Output B.
16 VIA
Logic Input A.
17 NIC
Not Internally Connected. Leave this pin floating.
18 NIC
Not Internally Connected. Leave this pin floating.
19 GND2 Ground 2. Ground reference for Isolator Side 2. Pin 11 and Pin 19 are internally connected, and connecting both to GND2 is
recommended.
20 VDD2
Supply Voltage for Isolator Side 2 (2.25 V to 3.6 V). Connect a ceramic bypass capacitor in the range of 0.01 µF to
0.1 µF between VDD2 (Pin 20) and GND2 (Pin 19).
1 Reference AN-1109 for specific layout guidelines.
Rev. 0 | Page 11 of 20
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11 Page | ||
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