PDF K4T51083QJ Data sheet ( Hoja de datos )

Número de pieza	K4T51083QJ
Descripción	512Mb J-die DDR2 SDRAM
Fabricantes	Samsung
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No Preview Available ! Rev. 1.1, Jul. 2011 K4T51043QJ K4T51083QJ K4T51163QJ 512Mb J-die DDR2 SDRAM 60 & 84FBGA with Lead-Free & Halogen-Free (RoHS compliant) datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2011 Samsung Electronics Co., Ltd. All rights reserved. -1- 1 page K4T51043QJ K4T51083QJ K4T51163QJ datasheet 3. Package pinout/Mechanical Dimension & Addressing 3.1 x4 Package Pinout (Top view) : 60ball FBGA Package 12 3 789 VDD NC VDDQ NC VDDL NC VSS VDD NC VSSQ DQ1 VSSQ VREF CKE BA0 A10/AP A3 A7 A12 VSS DM VDDQ DQ3 VSS WE BA1 A1 A5 A9 NC A B C D E F G H J K L VSSQ DQS VDDQ DQ2 VSSDL RAS CAS A2 A6 A11 NC DQS VSSQ DQ0 VSSQ CK CK CS A0 A4 A8 A13 NOTE : 1. Pin B3 has identical capacitance as pin B7. 2. VDDL and VSSDL are power and ground for the DLL. VDDQ NC VDDQ NC VDD ODT VDD VSS Rev. 1.1 DDR2 SDRAM Ball Locations (x4) : Populated Ball + : Depopulated Ball Top View (See the als through the package) 123456789 A + ++ B + ++ C + ++ D + ++ E + ++ F+ + ++ G + ++ + H+ J + ++ + ++ + K+ + ++ L+ + ++ + -5- 5 Page K4T51043QJ K4T51083QJ K4T51163QJ 5. DDR2 SDRAM Addressing datasheet 512Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address 128Mb x4 4 BA0,BA1 A10/AP A0 ~ A13 A0 ~ A9,A11 * Reference information: The following tables are address mapping information for other densities. 64Mb x 8 4 BA0,BA1 A10/AP A0 ~ A13 A0 ~ A9 256Mb 1Gb 2Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address Configuration # of Bank Bank Address Auto precharge Row Address Column Address Configuration # of Bank Bank Address Auto precharge Row Address Column Address 4Gb Configuration # of Bank Bank Address Auto precharge Row Address Column Address 64Mb x4 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9,A11 256Mb x4 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9,A11 512Mb x4 8 BA0 ~ BA2 A10/AP A0 ~ A14 A0 ~ A9,A11 1 Gb x4 8 BA0 ~ BA2 A10/AP A0 - A15 A0 - A9,A11 32Mb x 8 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9 128Mb x 8 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9 256Mb x 8 8 BA0 ~ BA2 A10/AP A0 ~ A14 A0 ~ A9 512Mb x 8 8 BA0 ~ BA2 A10/AP A0 - A15 A0 - A9 Rev. 1.1 DDR2 SDRAM 32Mb x16 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A9 16Mb x16 4 BA0,BA1 A10/AP A0 ~ A12 A0 ~ A8 64Mb x16 8 BA0 ~ BA2 A10/AP A0 ~ A12 A0 ~ A9 128Mb x16 8 BA0 ~ BA2 A10/AP A0 ~ A13 A0 ~ A9 256Mb x16 8 BA0 ~ BA2 A10/AP A0 - A14 A0 - A9 - 11 - 11 Page

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