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PDF HFBR-5301 Data sheet ( Hoja de datos )
| Número de pieza | HFBR-5301 | |
| Descripción | Fibre Channel 133 MBd and Fibre Channel 133 MBd and Cost 1x9 Package Style | |
| Fabricantes | Agilent(Hewlett-Packard) | |
| Logotipo | .gif "Agilent(Hewlett-Packard)"){kind=logo} |
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Fibre Channel 133 MBd and
266 MBd Transceivers in Low
Cost 1x9 Package Style
Technical Data
HFBR-5301 133 MBd
HFBR-5302 266 MBd
Features
• Full Compliance with ANSI
X3T11 Fibre Channel
Physical and Signaling
Interface
• Multisourced 1x9 Package
Style with Duplex SC
Connector
• Wave Solder and Aqueous
Wash Process Compatibility
• Compatible with Various
Manufacturers FC-0 and
FC-1 Circuits
Applications
• Fibre Channel 12.5 MB/s
12-M6-LE-I Interfaces for
1300 nm LED Links to
1500 m
• Fibre Channel 25 MB/s
25-M6-LE-I Interfaces for
1300 nm LED Links to
1500 m
Description
The HFBR-5301 and HFBR-5302
Fibre Channel Transceivers from
Hewlett-Packard provide the
system designer with products to
implement Fibre Channel designs
for use in multimode fiber (MMF)
applications. These include the
12.5 MB/sec 12-M6-LE-I interface
and the 25 MB/sec 25-M6-LE-I
interface for 1300 nm LED links.
5963-5608E (3/95)
The products are produced in the
new industry standard 1x9 SIP
package style with a duplex SC
connector interface as defined in
the Fiber Channel ANSI FC-PH
standard document.
The HFBR-5301 is a 1300 nm
transceiver specified for use in
133 MBd, 12.5 MB/s, 12-M6-LE-I
Fibre Channel interfaces to either
62.5/125 µm or 50/125 µm
multimode fiber-optic cables.
The HFBR-5302 is a 1300 nm
transceiver specified for use in
266 MBd, 25 MB/s, 25-M6-LE-I
Fibre Channel interfaces to either
62.5/125 µm or 50/125 µm
multimode fiber-optic cables.
Transmitter Sections
The transmitter sections of the
HFBR-5301 and HFBR-5302
utilize 1300 nm InGaAsP LEDs.
These LEDs are packaged in the
optical subassembly portion of
the transmitter section. They are
driven by a custom silicon IC
which converts PECL logic
signals, into an analog LED drive
current.
Receiver Sections
The receiver sections of the
HFBR-5301 and HFBR-5302
utilize InGaAs PIN photo diodes
coupled to a custom silicon
transimpedance preamplifier IC.
These are packaged in the optical
subassembly portion of the
receiver.
These PIN/preamplifier combina-
tions are coupled to a custom
quantizer IC which provides the
final pulse shaping for the logic
output and the Signal Detect
function. The Data output is
differential. The Signal Detect
output is single-ended. Both data
and signal detect outputs are
PECL compatible, ECL refer-
enced (shifted) to a +5 volt
power supply.
Package
The overall package concept for
the HP Fibre Channel trans-
ceivers consists of three basic
elements; the two optical
subassemblies, an electrical
subassembly and the housing
with integral duplex SC connec-
tor interface. This is illustrated in
the block diagram in Figure 1.
215
1 page  
plane be provided in the circuit
board directly under the
transceiver to provide a low
inductance ground for signal
return current. This recommen-
dation is in keeping with good
high frequency board layout
practices.
Board Layout - Hole Pattern
The Hewlett-Packard transceiver
complies with the circuit board
“Common Transceiver Footprint”
hole pattern defined in the
original multisource announce-
ment for the 1x9 pin package
style. This drawing is reproduced
in Figure 7 with the addition of
ANSI Y14.5M compliant dimen-
sioning to be used as a guide in
the mechanical layout of your
circuit board.
Board Layout – Art Work
The Applications Engineering
group has developed Gerber file
art work for a multilayer printed
circuit board layout incorporating
the recommendations above.
Contact your local Hewlett-
Packard sales representative for
details.
Regulatory Compliance
These transceiver products are
intended to enable system
designers to develop equipment
that complies with the various
international regulations govern-
ing certification of Information
Technology Equipment. See the
Regulatory Compliance Table for
details.
Electromagnetic Interference
(EMI)
Most equipment designs utilizing
these high-speed transceivers
from Hewlett-Packard will need
to meet the requirements of the
FCC in the United States,
CENELEC EN55022 (CISPR 22)
in Europe and VCCI in Japan.
The HFBR-5301 and HFBR-5302
are suitable for use in designs
ranging from a single transceiver
in a desktop computer to large
quantities of transceivers in a
hub, switch or concentrator.
Electrostatic Discharge (ESD)
There are two design cases in
which immunity to ESD damage
is important.
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TOP VIEW
The first case is during handling
of the transceiver prior to mount-
ing it on the circuit board. You
should use normal ESD handling
precautions for ESD sensitive
devices. These precautions
include using grounded wrist
straps, work benches, and floor
mats in ESD controlled areas.
The second case to consider is
static discharges to the exterior
of the equipment chassis contain-
ing the transceiver parts. To the
extent that the transceiver duplex
SC connector is exposed to the
outside of the equipment chassis,
it may be subject to whatever
ESD system level test criteria that
the equipment is intended to
meet.
Immunity
Equipment utilizing these trans-
ceivers will be subject to radio-
frequency electromagnetic fields
in some environments. These
transceivers have a high immunity
to such fields (see AN1075,
“Testing and Measuring Electro-
magnetic Compatibility Perfor-
mance of the HFBR-510X/520X
Fiber-Optic Transceivers,” 5963-
3358E).
Transceiver Reliability and
Performance Qualification
Data
The 1x9 transceivers have passed
Hewlett-Packard reliability and
performance qualification testing
and are undergoing ongoing
quality monitoring. Details are
available from your Hewlett-
Packard sales representative.
These transceivers are manu-
factured at the Hewlett-Packard
Singapore location which is an
ISO 9002 certified facility.
Figure 7. Recommended Board Layout Hole Pattern.
219
5 Page 
Notes:
1. This is the maximum voltage that
can be applied across the
Differential Transmitter Data Inputs
to prevent damage to the input ESD
protection circuit.
2. When component testing these
products do not short the receiver
data or signal detect outputs directly
to ground to avoid damage to the
part.
3. The outputs are terminated with 50
Ω connected to VCC - 2 V.
4. The power supply current needed to
operate the transmitter is provided
to differential ECL circuitry. This
circuitry maintains a nearly constant
current flow from the power supply.
Constant current operation helps to
prevent unwanted electrical noise
from being generated and conducted
or emitted to neighboring circuitry.
5. These optical power values are
measured as follows:
• The Beginning of Life (BOL) to
the End of Life (EOL) optical
power degradation is typically 1.5
dB per the industry convention for
long wavelength LEDs. The actual
degradation observed in Hewlett-
Packard’s 1300 nm LED products
is < 1 dB as specified in this data
sheet.
• Over the specified operating
voltage and temperature ranges.
• With 25 MBd (12.5 MHz square-
wave) input signal.
• At the end of one meter of noted
optical fiber with cladding modes
removed.
The average power value can be
converted to a peak power value by
adding 3 dB. Higher output optical
power transmitters are available on
special request.
6. The Extinction Ratio is a measure of
the modulation depth of the optical
signal. The data “0” output optical
power is compared to the data “1”
peak output optical power and
expressed as a percentage. With the
transmitter driven by a 12.5 MHz
square-wave signal, the average
optical power is measured. The data
“1” peak power is then calculated by
adding 3dB to the measured average
optical power. The data “0” output
optical power is found by measuring
the optical power when the transmit-
ter is driven by a logic “0” input. The
extinction ratio is the ratio of the
optical power at the “0” level com-
pared to the optical power at the “1”
level expressed as a percentage or in
decibels.
7. This parameter complies with the
requirements for the tradeoffs
between center wave-length, spectral
width, and rise/fall times shown in
Figure 8.
8. The optical rise and fall times are
measured from 10% to 90% when
the transmitter is driven by a 25
MBd (12.5 MHz square-wave) input
signal. This parameter complies with
the requirements for the tradeoffs
between center wavelength, spectral
width, and rise/fall times shown in
Figure 8.
8.a. The optical rise and fall times are
measured from 10% to 90% when
the transmitter is driven by a 25
MBd (12.5 MHz square-wave) input
signal.
9. Deterministic Jitter is defined as the
combination of Duty Cycle
Distortion and Data Dependent
Jitter. Deterministic Jitter is
measured with a test pattern
consisting of repeating K28.5
(00111110101100000101) data
bytes and evaluated per the method
in FC-PH Annex A.4.3.
10. Random Jitter is specified with a
sequence of K28.7 (square wave of
alternating 5 ones and 5 zeros) data
bytes and evaluated at a Bit Error
Ratio (BER) of 1 x 10-12 per the
method in FC-PH Annex A.4.4.
11. This specification is intended to
indicate the performance of the
receiver section of the transceiver
when Input Optical Power signal
characteristics are present per the
following definitions. The Input
Optical Power dynamic range from
the minimum level (with a window
time-width) to the maximum level is
the range over which the receiver is
specified to provide output data with
a Bit Error Rate (BER) better than
or equal to 1 x 10-12.
• At the Beginning of Life (BOL)
• Over the specified operating tem-
perature and voltage ranges.
• Input is a 266 MBd, 27 - 1
psuedorandom data pattern.
• Receiver data window time-width
is ± 0.94 ns or greater and
centered at mid-symbol. This data
window time width is calculated to
simulate the effect of worst case
input jitter per FC-PH Annex J
and clock recovery sampling
position in order to insure good
operation with the various FC-0
receiver circuits.
• The integral transmitter is operat-
ing with a 266 MBd, 133 MHz
square-wave, input signal to simu-
late any cross-talk present
between the transmitter and
receiver sections of the
transceiver.
• The maximum total jitter added by
the receiver and the maximum
total jitter presented to the clock
recovery circuit comply with the
maximum limits listed in Annex J,
but the allocations of the Rx
added jitter between deterministic
jitter and random jitter are
different than in Annex J.
11a. Same as Note 11 except:
• The receiver input signal is a 133
MBd, 27 - 1 psuedorandom data
patter.
• The integral transmitter is operat-
ing with a 133 MBd, 66.5 MHz
square wave.
• The receiver data window width
is ± 1.73 ns.
• The receiver added jitter maxi-
mums and allocations are
identical to the limits listed in
Annex J.
12. All conditions of Note 11 apply
except that the measurement is
made at the center of the symbol
with no window time-width.
12a. All conditions of Note 11a apply
except that the measurement is
made at the center of the symbol
with no window time-width.
13. This value is measured during the
transition from low to high levels of
input optical power.
14. This value is measured during the
transition from high to low levels of
input optical power.
15. These values are measured with the
outputs terminated into 50 Ω
connected to VCC - 2 V and an input
optical power level of -14 dBm
average.
16. The power dissipation value is the
power dissipated in the receiver
itself. Power dissipation is calculated
as the sum of the products of supply
voltage and supply current, minus
225
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HFBR-5301.PDF ] | |
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