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PDF HFA3860A Data sheet ( Hoja de datos )
| Número de pieza | HFA3860A | |
| Descripción | Direct Sequence Spread Spectrum Baseband | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HFA3860A
November 1998 File Number 4488.2
Direct Sequence Spread Spectrum
Baseband
™ The Intersil HFA3860A Direct
Sequence Spread Spectrum (DSSS)
baseband processor is part of the
PRISM™ 2.4GHz radio chipset, and
contains all the functions necessary for
a full or half duplex packet baseband transceiver.
The HFA3860A has on-board A/Ds for analog I and Q inputs,
for which the HFA3724/6 IF QMODEM is recommended.
Differential phase shift keying modulation schemes DBPSK
and DQPSK, with data scrambling capability, are available
along with M-Ary Bi-Orthogonal Keying to provide a variety
of data rates. Built-in flexibility allows the HFA3860A to be
configured through a general purpose control bus, for a
range of applications. A Receive Signal Strength Indicator
(RSSI) monitoring function with on-board 6-bit A/D provides
Clear Channel Assessment (CCA) to avoid data collisions
and optimize network throughput. The HFA3860A is housed
in a thin plastic quad flat package (TQFP) suitable for
PCMCIA board applications.
Ordering Information
PART NO.
TEMP.
RANGE (oC)
PKG. TYPE PKG. NO.
HFA3860AIV
-40 to 85 48 Ld TQFP Q48.7x7
HFA3860AIV96
-40 to 85 Tape and Reel
Pinout
HFA3860A (TQFP)
TEST_CK
TX_PE
TXD
TXCLK
TX_RDY
GND
VDD
R/W
CS
VDDA
GND
IIN
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
1213
14
15
16
17
18
19
20
21 22
23
25
24
RXCLK
RXD
MD_RDY
RX_PE
CCA
GND
MCLK
VDD
RESET
ANTSEL
ANTSEL
SD
Features
• Complete DSSS Baseband Processor
• Processing Gain . . . . . . . . . . . . . . . . . . . . . . . . . . ≥10.4dB
• Programmable Data Rate. . . . . . . .1, 2, 5.5, and 11MBPS
• Ultra Small Package . . . . . . . . . . . . . . . . . . . . 7 x 7 x 1mm
• Single Supply Operation (44MHz Max) . . . . . 2.7V to 3.6V
• Modulation Methods . . . . . . .DBPSK, DQPSK, and MBOK
• Supports Full or Half Duplex Operations
• On-Chip A/D Converters for I/Q Data (3-Bit, 22MSPS) and
RSSI (6-Bit)
• Backwards Compatible with HFA3860
• Supports Antenna Diversity
Applications
• Enterprise WLAN Systems
• Systems Targeting Ethernet Data Rates
• DSSS PCMCIA Wireless Transceiver
• Spread Spectrum WLAN RF Modems
• TDMA Packet Protocol Radios
• Part 15 Compliant Radio Links
• Portable Bar Code Scanners/POS Terminal
• Portable PDA/Notebook Computer
• Wireless Digital Audio
• Wireless Digital Video
• PCN/Wireless PBX
IIN
QIN
RSSI
IOUT
SIMPLIFIED BLOCK DIAGRAM
3-BIT
A/D
DEMOD.
3-BIT
A/D
6-BIT
A/D
CCA
PRO-
CESSOR
INTER-
FACE
CTRL
QOUT
MOD.
2-131
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
1 page  
HFA3860A
Pin Descriptions (Continued)
NAME
PIN TYPE I/O
DESCRIPTION
TXD
3
I TXD is an input, used to transfer MAC Payload Data Unit (MPDU) data from the MAC or network
processor to the HFA3860A. The data is received serially with the LSB first. The data is clocked in the
HFA3860A at the rising edge of TXCLK.
TXCLK
4
O TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to
the HFA3860A, synchronously. Transmit data on the TXD bus is clocked into the HFA3860A on the
rising edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the
clock will be dependent upon the data rate that is programmed in the signalling field of the header.
TX_RDY
5
O TX_RDY is an output to the external network processor indicating that Preamble and Header
information has been generated and that the HFA3860A is ready to receive the data packet from the
network processor over the TXD serial bus. The TX_RDY returns to the inactive state when the last chip
of the last symbol has been output.
CCA 32 O Clear Channel Assessment (CCA) is an output used to signal that the channel is clear to transmit. The
CCA algorithm makes its decision as a function of RSSI, Energy detect (ED), and Carrier Sense (CRS).
The CCA algorithm and its features are described elsewhere in the data sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).
This polarity is programmable and can be inverted.
RXD 35 O RXD is an output to the external network processor transferring demodulated Header information and
data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with MD_RDY.
RXCLK
36
O RXCLK is the bit clock output. This clock is used to transfer Header information and payload data through
the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is held to a
logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been detected.
Data should be sampled on the rising edge. This polarity is programmable and can be inverted.
MD_RDY
34
O MD_RDY is an output signal to the network processor, indicating header data and a data packet are
ready to be transferred to the processor. MD_RDY is an active high signal and it envelopes the data
transfer over the RXD serial bus. MD_RDY goes active when the SFD is detected and returns to its
inactive state when RX_PE goes inactive or an error is detected in the header.
RX_PE
33
I When active, the receiver is configured to be operational, otherwise the receiver is in standby mode.
This is an active high input signal. In standby, RX_PE inactive, all A/D converters are disabled.
SD 25 I/O SD is a serial bidirectional data bus which is used to transfer address and data to/from the internal registers.
The bit ordering of an 8-bit word is MSB first. The first 8 bits during transfers indicate the register address
immediately followed by 8 more bits representing the data that needs to be written or read at that register.
SCLK
24
I SCLK is the clock for the SD serial bus. The data on SD is clocked at the rising edge. SCLK is an input
clock and it is asynchronous to the internal master clock (MCLK). The maximum rate of this clock is
11MHz or one half the master clock frequency, whichever is lower.
SDI 23 I Serial Data Input in 3 wire mode described in Tech Brief 362. This pin is not used in the 4 wire interface
described in this data sheet. It should not be left floating.
R/W 8
I R/W is an input to the HFA3860A used to change the direction of the SD bus when reading or writing
data on the SD bus. R/W also enables the serial shift register used in a read cycle. R/W must be set up
prior to the rising edge of SCLK. A high level indicates read while a low level is a write.
CS 9 I CS is a Chip Select for the device to activate the serial control port. The CS doesn’t impact any of the
other interface ports and signals, i.e., the TX or RX ports and interface signals. This is an active low
signal. When inactive SD, SCLK, and R/W become “don’t care” signals.
TEST 7:0
37, 38, 39,
40, 43, 44,
45, 46
O This is a data port that can be programmed to bring out internal signals or data for monitoring. These
bits are primarily reserved by the manufacturer for testing. A further description of the test port is given
at the appropriate section of this data sheet.
TEST_CK
1
O This is the clock that is used in conjunction with the data that is being output from the test bus (TEST 0-7).
RESET
28
I Master reset for device. When active TX and RX functions are disabled. If RESET is kept low the
HFA3860A goes into the power standby mode. RESET does not alter any of the configuration register
values nor does it preset any of the registers into default values. Device requires programming upon
power-up.
MCLK
30
I Master Clock for device. The nominal frequency of this clock is 44MHz. This is used internally to gen-
erate all other internal necessary clocks and is divided by 2 or 4 for the transceiver clocks.
IOUT 48 O TX Spread baseband I digital output data. Data is output at the chip rate.
QOUT
47
O TX Spread baseband Q digital output data. Data is output at the chip rate.
NOTE: Total of 48 pins; ALL pins are used.
2-135
5 Page 
HFA3860A
The interface specifications for the RSSI A/D are listed in
Table 4 below (VREFP = 1.75V).
TABLE 4. RSSI A/D SPECIFICATIONS
PARAMETER
MIN TYP
Full Scale Input Voltage
--
Input Bandwidth (0.5dB)
1MHz
-
Input Capacitance
- 7pF
Input Impedance (DC)
1M -
MAX
1.15
-
-
-
Test Port
The HFA3860A provides the capability to access a number of
internal signals and/or data through the Test port, pins TEST
7:0. In addition pin 1 (TEST_CK) is an output that can be used
in conjunction with the data coming from the test port outputs.
The test port is programmable through configuration register
(CR28). Any signal on the test port can also be read from
configuration register (CR29) via the serial control port.
There are 32 modes assigned to the PRISM test port. Some
are only applicable to factory test.
TABLE 5. TEST MODES
MODE DESCRIPTION
0 Quiet Test Bus
1 RX Acquisition
Monitor
2 TX Field Monitor
3 RSSI Monitor
4 SQ1 Monitor
5 SQ2 Monitor
6
7
8
9
10
(0Ah)
11
12
Correlator Lo
Rate
Freq Test Lo
Rate
Phase Test Lo
Rate
NCO Test Lo
Rate
Bit Sync Accum
Lo Rate
Reserved
A/D Cal Test
Mode
TEST_CLK
TEST (7:0)
0 00
Initial Detect
A/DCal, CRS, ED,
Track, SFD Detect, Sig-
nal Field Ready, Length
Field Ready, Header
CRC Valid
IQMARK
A/DCal, TXPE Internal,
Preamble Start, SFD
Start, Signal Field
Start, Length Field
Start, CRC Start,
MPDU Start
RSSI Pulse CSE Latched, CSE,
RSSI Out (5:0)
Pulse after SQ1 (7:0)
SQ is valid
Pulse after SQ2 (7:0)
SQ is valid
Sample CLK Correlator Magnitude
(7:0)
Subsample Frequency Register
CLK (18:11)
Subsample Phase Register (7:3)
CLK Shift <2:0>
Subsample NCO Register (15:8)
CLK
Enable
Bit Sync Accum (7:3)
Shift (2:0)
Reserved Factory Test Only
A/D Cal CLK A/DCal, ED, A/DCal
Disable, ADCal (4:0)
TABLE 5. TEST MODES (Continued)
MODE DESCRIPTION TEST_CLK
TEST (7:0)
13 Correlator I High Sample CLK Correlator I (8:1)
Rate
14 Correlator Q High Sample CLK Correlator Q (8:1)
Rate
15 Chip Error
Accumulator
0
Chip Error Accum
(14:7)
16 NCO Test Hi
Rate
Sample CLK NCO Accum (19:12)
17 Freq Test Hi Rate Sample CLK Lag Accum (18:11)
18 Carrier Phase
Error Hi Rate
Sample CLK Carrier Phase Error
(6,6:0)
19 Reserved
Sample CLK Factory Test Only
20 Reserved
Sample CLK Factory Test Only
21 I_A/D, Q_A/D
Sample CLK 0,0,I_A/D (2:0),Q_A/D
(2:0)
22 Reserved
Reserved Factory Test Only
23 Reserved
Reserved Factory Test Only
24 Reserved
Reserved Factory Test Only
25 A/D Cal Accum A/D Cal
Lo Accum (8)
A/D Cal Accum (7:0)
26 A/D Cal Accum Hi A/D Cal
A/D Cal Accum (16:9)
Accum (17)
27 Freq Accum Lo Freq Accum Freq Accum (14:7)
(15)
28 Reserved
Reserved Factory Test Only
29 SQ2 Monitor Hi Pulse After SQ2 (15:8)
SQ Valid
30-31 Reserved
Reserved Factory Test Only
Definitions
ED. Energy Detect, indicates that the RSSI value exceeds its
programmed threshold.
CRS. Carrier Sense, indicates that a signal has been
acquired (PN acquisition).
TXCLK. Transmit clock.
Track. Indicates start of tracking and start of SFD time-out.
SFD Detect. Variable time after track starts.
Signal Field Ready. ~ 8µs after SFD detect.
Length Field Ready. ~ 32µs after SFD detect.
Header CRC Valid. ~ 48µs after SFD detect.
DCLK. Data bit clock.
FrqReg. Contents of the NCO frequency register.
PhaseReg. phase of signal after carrier loop correction.
NCO PhaseAccumReg. Contents of the NCO phase
accumulation register.
SQ1. Signal Quality measure #1. Contents of the bit sync
accumulator. Eight MSBs of most recent 16-bit stored value.
2-141
11 Page | ||
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| PDF Descargar | [ Datasheet HFA3860A.PDF ] | |
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