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PDF HFA3724IN Data sheet ( Hoja de datos )
| Número de pieza | HFA3724IN | |
| Descripción | 400MHz Quadrature IF Modulator/Demodulator | |
| Fabricantes | Intersil Corporation | |
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Data Sheet
HFA3724
November 1999 File Number 4067.7
400MHz Quadrature IF
Modulator/Demodulator
™ The Intersil 2.4GHz PRISM™ chip set is a
highly integrated five-chip solution for RF
modems employing Direct Sequence
Spread Spectrum (DSSS) signaling. The
HFA3724 400MHz Quadrature IF
Modulator/Demodulator is one of the five chips in the PRISM™
chip set (see the Typical Application Diagram).
The HFA3724 is a highly integrated baseband converter for
quadrature modulation applications. It features all the necessary
blocks for baseband modulation and demodulation of I and Q
signals. It has a two stage integrated limiting IF amplifier with 84db
of gain with a built in Receive Signal Strength Indicator (RSSI).
Baseband antialiasing and shaping filters are integrated in the
design. Four filter bandwidths are programmable via a two bit
digital control interface. In addition, these filters are continuously
tunable over a ±20% frequency range via one external resistor. The
modulator channel receives digital I and Q data for processing. To
achieve broadband operation, the Local Oscillator frequency input
is required to be twice the desired frequency of
modulation/demodulation. A selectable buffered divide by 2 LO
output and a stable reference voltage are provided for convenience
of the user. The device is housed in a thin 80 lead TQFP package
well suited for PCMCIA board applications.
Ordering Information
PART NUMBER
HFA3724IN
HFA3724IN96
TEMP. RANGE
(oC)
-40 to 85
-40 to 85
PACKAGE
80 Ld TQFP
Tape and Reel
PKG. NO.
Q80.14x14
Simplified Block Diagram
Features
• Integrates all IF Transmit and Receive Functions
• Broad Frequency Range . . . . . . . . . . . 10MHz to 400MHz
• I/Q Amplitude and Phase Balance . . . . . . . . . . . 0.2dB, 2o
• 5th Order Programmable
Low Pass Filter. . . . . . . . . . . . . . . . . . . 2.2MHz - 17.6MHz
• 400MHz Limiting IF Gain Strip with RSSI. . . . . . . . . .84dB
• Low LO Drive Level . . . . . . . . . . . . . . . . . . . . . . . -15dBm
• Fast Transmit-Receive Switching . . . . . . . . . . . . . . . . . 1µs
• Power Management/Standby Mode
• Single Supply 2.7V to 5.5V Operation
Applications
• Systems Targeting IEEE 802.11 Standard
• TDD Quadrature-Modulated Communication Systems
• Wireless Local Area Networks
• PCMCIA Wireless Transceivers
• ISM Systems
• TDMA Packet Protocol Radios
• PCS/Wireless PBX
• Wireless Local Loop
LIM1_IN
RSSI1
RSSI2
IF
MOD_LO_IN
MOD_LO_OUT
LO_GND
MOD_TX_IF_OUT
2V
REF
IF
I
÷2
0o/90o
M
U
X
Q
∑
M
U
X
LPF_RXI_OUT
LPF_RXQ _OUT
LPF_TXI_IN
LPF_TXQ_IN
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
PRISM® is a registered trademark of Intersil Corporation. PRISM logo is a trademark of Intersil Corporation.
1 page  
HFA3724
Typical Application Diagram (Targeting IEEE 802.11 Standard)
TOYOCOM
TQS 432
VCC
0.1
75
(NOTE 2)
(NOTE 1)
100p 2
PE
74
77
100p
VCC
0.1
55
PE
54
57 100p
3
0.1 1 4
76
80
47p
79
560 62
0.1 63
56 1K
100p 61 64
60 100p
100p
100p
47p
59
VCC
0.1
0.1 VCC
45
48
49
47
33 0.01 30
34 29
0.01
35 0.01 28
36 27
9
LO_IN
(NOTE 3)
47p 220 44
56
0.01
18
900
19
(NOTE 5)
TOYOCOM
TQS 432
(NOTE 6)
100p 47 46
0.1 VCC
47nH
TX_IF_OUT
316
42
100p (NOTE 4)
50
NC
0.01
37 26
38 25
0.01
39 0.01 24
40 23
0.01
RSSI
RXI_OUT
14 0.01
RXQ_OUT
15 0.01
20
16 LPF_SEL1
VCC
17 LPF_SEL0
10
2V REF
0.1
12 TXI
4.3K
680
0.1
11
680
TXQ
13 4.3K
VCO
560MHz
VCO (AUXILIARY)
43 41
22 21
DUAL SYNTHESIZER
HFA3524IA
TYPICAL APPLICATION DIAGRAM (TARGETING IEEE 802.11 STANDARD)
NOTES:
1. Input termination used to match a SAW filter.
2. Typical bandpass filter for 280MHz, BW = 47MHz, Q = 6. Can also be used if desired after the second stage.
3. Network shown for a typical -10dBm input at 50Ω.
4. Output termination used to match a SAW filter.
5. RTUNE value for a 7.7MHz cutoff frequency setting.
6. LO buffer output termination is needed only when the buffer is enabled by pin 50 connected to GND, otherwise tie pin 46 to pin 47.
5
5 Page 
HFA3724
Typical Performance Curves, Demodulator (See Figure 23 Test Diagram)
10mA/DIV.
50mV/DIV.
90
85o 400
25o
-40o
10
2.5 4.0 5.5
VCC
FIGURE 1. DEMODULATOR SUPPLY CURRENT vs VCC AND
TEMPERATURE
40mV/DIV.
700
85o
25o
-40o
500
100
VCC = 3V
-100
-80 -60 -40 -20
INPUT POWER (dBm INTO 50Ω)
0
FIGURE 2. DEMODULATOR I/Q OUTPUT SWING vs INPUT
POWER
1dBm/DIV.
-80
85o
-85 25o
-40o
300
2.5
4.0
VCC
5.5
FIGURE 3. DEMOD I/Q OUTPUT SWING vs VCC AND
TEMPERATURE
0.2o/DIV.
+1o
-90
2.5
4.0
VCC
5.5
FIGURE 4. CASCADED LIMITER -3dB INPUT SENSITIVITY
RESPONSE vs VCC AND TEMPERATURE
0.1dB/DIV.
+0.4dB
0o EXPECTED VARIATION
WINDOW vs VCC
0.0dB
EXPECTED VARIATION
WINDOW vs VCC
-1o
2.5
4.0
VCC
5.5
FIGURE 5. DEMOD I/Q PHASE BALANCE VARIATION vs VCC
-0.4dB
2.5
4.0
VCC
5.5
FIGURE 6. DEMOD I/Q AMPLITUDE BALANCE VARIATION vs VCC
11
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