PDF HYMP125P72CP4L-S6 Data sheet ( Hoja de datos )

Número de pieza	HYMP125P72CP4L-S6
Descripción	240pin DDR2 VLP Registerd DIMMs based on 1Gb C version
Fabricantes	Hynix Semiconductor
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No Preview Available ! 240pin DDR2 VLP Registerd DIMMs based on 1Gb C version This Hynix DDR2 VLP(Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb C ver- sion DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 1Gb C ver- sion based VLP Registered DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. ORDERING INFORMATION Part Name Density Org. Component Configuration Ranks Parity Support HYMP112P72CP8L-C4/Y5/S6 HYMP125P72CP4L-C4/Y5/S6 HYMP351P72CMP4L-C4/Y5/S6 HYMP41GP72CNP4L-C4/Y5 1GB 2GB 4GB 8GB 128Mbx72 128Mbx8(HY5PS1G821CFP)9 256Mbx72 256Mbx4(HY5PS1G421CFP)18 512Mbx72 512Mbx4(HY5PS2G421CMP)18 1Gbx72 1Gbx4(HY5PS4G421CNP)18 1 1 2 4 O O O O Note: 1. “P” of part number[12th digit] stands for Lead free products. SPEED GRADE & KEY PARAMETERS Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL6 CL-tRCD-tRP C4 (DDR2-533) 400 533 - - 4-4-4 Y5 (DDR2-667) 400 533 667 - 5-5-5 S6 (DDR2-800) - 400 533 800 6-6-6 Unit Mbps Mbps Mbps Mbps tCK This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.2 / May. 2008 1 Free Datasheet http://www.datasheet4u.com/ 1 page 1240pin DDR2 VLP Registered DIMMs PIN ASSIGNMENT Pin Name Pin Name Pin Name Pin Name Pin Name Pin Name 1 VREF 41 VSS 81 DQ33 121 VSS 161 CB4 201 VSS 2 VSS 42 CB0 82 VSS 122 DQ4 162 CB5 202 DM4/DQS13 3 DQ0 43 CB1 83 DQS4 123 DQ5 163 VSS 203 DQS13 4 DQ1 44 VSS 84 DQS4 124 VSS 164 DM8,DQS17 204 VSS 5 VSS 45 DQS8 85 VSS 125 DM0/DQS9 165 DQS17 205 DQ38 6 DQS0 46 DQS8 86 DQ34 126 DQS9 166 VSS 206 DQ39 7 DQS0 47 VSS 87 DQ35 127 VSS 167 CB6 207 VSS 8 VSS 48 CB2 88 VSS 128 DQ6 168 CB7 208 DQ44 9 DQ2 49 CB3 89 DQ40 129 DQ7 169 VSS 209 DQ45 10 DQ3 50 VSS 90 DQ41 130 VSS 170 VDDQ 210 VSS 11 VSS 51 VDDQ 91 VSS 131 DQ12 171 NC,CKE1 211 DM5/DQS14 12 DQ8 52 CKE0 92 DQS5 132 DQ13 172 VDD 212 DQS14 13 DQ9 53 VDD 93 DQS5 133 VSS 173 A15,NC 213 VSS 14 VSS 54 BA2,NC 94 VSS 134 DM1/DQS10 174 A14,NC 214 DQ46 15 DQS1 55 NC,Err_Out 95 DQ42 135 DQS10 175 VDDQ 215 DQ47 16 DQS1 56 VDDQ 96 DQ43 136 VSS 176 A12 216 VSS 17 VSS 57 A11 97 VSS 137 RFU 177 A9 217 DQ52 18 RESET 58 A7 98 DQ48 138 RFU 178 VDD 218 DQ53 19 NC 59 VDD 99 DQ49 139 VSS 179 A8 219 VSS 20 VSS 60 A5 100 VSS 140 DQ14 180 A6 220 RFU 21 DQ10 61 A4 101 SA2 141 DQ15 181 VDDQ 221 RFU 22 DQ11 62 VDDQ 102 NC(TEST) 142 VSS 182 A3 222 VSS 23 VSS 63 A2 103 VSS 143 DQ20 183 A1 223 DM6/DQS15 24 DQ16 64 VDD 104 DQS6 144 DQ21 184 VDD 224 NC,DQS15 25 DQ17 Key 105 DQS6 145 VSS Key 225 VSS 26 VSS 65 VSS 106 VSS 146 DM2/DQS11 185 CK0 226 DQ54 27 DQS2 66 VSS 107 DQ50 147 DQS11 186 CK0 227 DQ55 28 DQS2 67 VDD 108 DQ51 148 VSS 187 VDD 228 VSS 29 VSS 68 NC,Err_Out 109 VSS 149 DQ22 188 A0 229 DQ60 30 DQ18 69 VDD 110 DQ56 150 DQ23 189 VDD 230 DQ61 31 DQ19 70 A10/AP 111 DQ57 151 VSS 190 BA1 231 VSS 32 VSS 71 BA0 112 VSS 152 DQ28 191 VDDQ 232 DM7/DQS16 33 DQ24 72 VDDQ 113 DQS7 153 DQ29 192 RAS 233 NC,DQS16 34 DQ25 73 WE 114 DQS7 154 VSS 193 S0 234 VSS 35 VSS 74 CAS 115 VSS 155 DM3/DQS12 194 VDDQ 235 DQ62 36 DQS3 75 VDDQ 116 DQ58 156 DQS12 195 ODT0 236 DQ63 37 DQS3 76 NC, S1 117 DQ59 157 VSS 196 A13,NC 237 VSS 38 VSS 77 NC, ODT1 118 VSS 158 DQ30 197 VDD 238 VDDSPD 39 DQ26 78 VDDQ 119 SDA 159 DQ31 198 VSS 239 SA0 40 DQ27 79 VSS 120 SCL 160 VSS 199 DQ36 240 SA1 80 DQ32 200 DQ37 NC= No Connect, RFU= Reserved for Future Use. Note: 1. RESET(Pin 18) is connected to both OE of PLL and Reset of register. 2. NC/Err_out (Pin 55) and NC/Par_In(Pin68) are for optional function to check address and command parity. 3. The Test pin(Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules(DIMMs) Rev. 0.2 / May. 2008 Free Datasheet http://www.datasheet4u.com/ 5 Page INPUT DC LOGIC LEVEL 1240pin DDR2 VLP Registered DIMMs Parameter Symbol Input High Voltage Input Low Voltage VIH(DC) VIL(DC) INPUT AC LOGIC LEVEL Min VREF + 0.125 -0.30 Max VDDQ + 0.3 VREF - 0.125 Unit V V Notes Parameter AC Input logic High AC Input logic Low Symbol VIH(AC) VIL(AC) DDR2 400/533 Min Max VREF + 0.250 - - VREF - 0.250 DDR2 667/800 Min Max VREF + 0.200 - - VREF - 0.200 Unit V V Notes AC INPUT TEST CONDITIONS Symbol VREF VSWING(MAX) SLEW Condition Input reference voltage Input signal maximum peak to peak swing Input signal minimum slew rate Value 0.5 * VDDQ 1.0 1.0 Units V V V/ns Notes 1 1 2, 3 Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac) on the negative transitions. VSWING(MAX) delta TF Falling Slew = VREF - VIL(ac) max delta TF delta TR VDDQ VIH(ac) min VIH(dc) min VREF VIL(dc) max VIL(ac) max VSS Rising Slew = VIH(ac)min - VREF delta TR Rev. 0.2 / May. 2008 < Figure : AC Input Test Signal Waveform> Free Datasheet http://www.datasheet4u.com/ 11 Page

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