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PDF AD5122 Data sheet ( Hoja de datos )
| Número de pieza | AD5122 | |
| Descripción | (AD5122 / AD5142) Nonvolatile Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Dual Channel, 128-/256-Position, SPI,
Nonvolatile Digital Potentiometer
AD5122/AD5142
FEATURES
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 µs
Linear gain setting mode
Single- and dual-supply operation
Independent logic supply: 1.8 V to 5.5 V
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm package option
4 kV ESD protection
APPLICATIONS
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
GENERAL DESCRIPTION
The AD5122/AD5142 potentiometers provides a nonvolatile
solution for 128-/256-position adjustment applications, offering
guaranteed low resistor tolerance errors of ±8% and up to ±6 mA
current density in the Ax, Bx, and Wx pins.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the RAW and RWB string resistors, allowing very accurate
resistor matching.
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making these
devices suitable for filter design.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows for pin-to-pin connection.
The wiper values can be set through an SPI-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
The AD5122/AD5142 is available in a compact, 16-lead, 3 mm ×
3 mm LFCSP and a 16-lead TSSOP. The parts are guaranteed to
operate over the extended industrial temperature range of −40°C
to +125°C.
FUNCTIONAL BLOCK DIAGRAM
VLOGIC
VDD
INDEP
POWER-ON
RESET
AD5122/
AD5142
RESET
SCLK
SDI
SYNC
SDO
SERIAL
INTERFACE 7/8
RDAC1
INPUT
REGISTER 1
RDAC2
INPUT
REGISTER 2
EEPROM
MEMORY
A1
W1
B1
A2
W2
B2
GND VSS
Figure 1.
Table 1. Family Models
Model
Channel Position
AD51231 Quad
128
AD5124 Quad
128
AD5124 Quad
128
AD51431 Quad
256
AD5144 Quad
256
AD5144 Quad
256
AD5144A Quad
256
AD5122 Dual
128
AD5122A Dual
128
AD5142 Dual
256
AD5142A Dual
256
AD5121 Single
128
AD5141 Single
256
Interface
I2C
SPI/I2C
SPI
I2C
SPI/I2C
SPI
I2C
SPI
I2C
SPI
I2C
SPI/I2C
SPI/I2C
Package
LFCSP
LFCSP
TSSOP
LFCSP
LFCSP
TSSOP
TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP/TSSOP
LFCSP
LFCSP
1 Two potentiometers and two rheostats.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2012 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
AD5122/AD5142
Parameter
DYNAMIC CHARACTERISTICS9
Bandwidth
Total Harmonic Distortion
Resistor Noise Density
VW Settling Time
Crosstalk (CW1/CW2)
Analog Crosstalk
Endurance10
Data Retention11
Symbol
BW
THD
eN_WB
tS
CT
CTA
Test Conditions/Comments Min
−3 dB
RAB = 10 kΩ
RAB = 100 kΩ
VDD/VSS = ±2.5 V, VA = 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ
RAB = 100 kΩ
Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ
RAB = 100 kΩ
VA = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
RAB = 10 kΩ
RAB = 100 kΩ
RAB = 10 kΩ
RAB = 100 kΩ
TA = 25°C
100
Typ1 Max
3
0.43
−80
−90
7
20
Unit
MHz
MHz
dB
dB
nV/√Hz
nV/√Hz
2 µs
12 µs
10 nV-sec
25 nV-sec
−90 dB
1 Mcycles
kcycles
50 Years
1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC).
9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
Rev. 0 | Page 5 of 32
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5 Page 
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to GND
VSS to GND
VDD to VSS
VLOGIC to GND
VA, VW, VB to GND
IA, IW, IB
Pulsed1
Frequency > 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
Frequency ≤ 10 kHz
RAW = 10 kΩ
RAW = 100 kΩ
Digital Inputs
Operating Temperature Range, TA3
Maximum Junction Temperature,
TJ Maximum
Storage Temperature Range
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Package Power Dissipation
ESD4
FICDM
Rating
−0.3 V to +7.0 V
+0.3 V to −7.0 V
7V
−0.3 V to VDD + 0.3 V or
+7.0 V (whichever is less)
VSS − 0.3 V, VDD + 0.3 V or
+7.0 V (whichever is less)
±6 mA/d2
±1.5 mA/d2
±6 mA/√d2
±1.5 mA/√d2
−0.3 V to VLOGIC + 0.3 V or
+7 V (whichever is less)
−40°C to +125°C
150°C
−65°C to +150°C
260°C
20 sec to 40 sec
(TJ max − TA)/θJA
4 kV
1.5 kV
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 d = pulse duty factor.
3 Includes programming of EEPROM memory.
4 Human body model (HBM) classification.
AD5122/AD5142
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 7. Thermal Resistance
Package Type
16-Lead LFCSP
16-Lead TSSOP
θJA
89.51
150.41
θJC
3
27.6
Unit
°C/W
°C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
Rev. 0 | Page 11 of 32
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5122.PDF ] | |
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