PDF HYMD264G726DF4N-D43 Data sheet ( Hoja de datos )

Número de pieza	HYMD264G726DF4N-D43
Descripción	184pin Registered DDR SDRAM DIMMs
Fabricantes	Hynix
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No Preview Available ! 184pin Registered DDR SDRAM DIMMs based on 256Mb D ver. (FBGA) This Hynix Registered Dual In-Line Memory Module (DIMM) series consists of 256Mb D ver. DDR SDRAMs in 60 ball FBGA package on a 184pin glass-epoxy substrate. This Hynix 256Mb D ver. based Registered DIMM series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. FEATURES • JEDEC Standard 184-pin dual in-line memory module (DIMM) • Two ranks 128M x 72, and One rank 64M x 72, 32M x 72 organization • Error Check Correction (ECC) Capability • 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 • All inputs and outputs are compatible with SSTL_2 interface • Fully differential clock operations (CK & /CK) with 166/200MHz • DLL aligns DQ and DQS transition with CK transition • Programmable CAS Latency: DDR333(2.5 clock), DDR400(3 clock) • Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode • Edge-aligned DQS with data outs and Center-aligned DQS with data inputs • Auto refresh and self refresh supported • 8192 refresh cycles / 64ms • Serial Presence Detect (SPD) with EEPROM • Built with 256Mb DDR SDRAMs in 60 ball FBGA pack- ages • JEDEC standard reference layout • Lead-free product listed for each configuration (RoHS compliant) ADDRESS TABLE 256MB 512MB 1GB Organization 32M x 72 64M x 72 128M x 72 Ranks 1 1 2 SDRAMs 32Mb x 8 64Mb x 4 64Mb x 4 # of DRAMs 9 18 36 # of row/bank/column Address 13(A0~A12)/2(BA0,BA1)/10(A0~A9) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) 13(A0~A12)/2(BA0,BA1)/11(A0~A9,A11) Refresh Method 8K / 64ms 8K / 64ms 8K / 64ms PERFORMANCE RANGE Part-Number Suffix Speed Bin CL - tRCD- tRP CL=3 Max Clock Frequency CL=2.5 CL=2 -D431 DDR400B 3-3-3 200 166 133 -J DDR333 2.5-3-3 - 166 133 Note: 1. 2.6V ± 0.1V VDD and VDDQ Power supply for DDR400 and 2.5V ± 0.2V for DDR333 Unit - CK MHz MHz MHz Rev. 1.1 / May.2005 1 This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Free Datasheet http://www.datasheet4u.com/ 1 page 184pin Registered DDR SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM 512MB, 64M x 72 ECC Registered DIMM: HYMD264G726DF[P]4N VSS /RS0 DQS0 DQS1 DQ0 DQ1 DQ2 DQ3 DQS2 DQ8 DQ9 DQ10 DQ11 DQS3 DQ16 DQ17 DQ18 DQ19 DQS4 DQ24 DQ25 DQ26 DQ27 DQS5 DQ32 DQ33 DQ34 DQ35 DQS6 DQ40 DQ41 DQ42 DQ43 DQS7 DQ48 DQ49 DQ50 DQ51 DQS8 DQ56 DQ57 DQ58 DQ59 CB0 CB1 CB2 CB3 DQS I/O0 I/O1 I/O2 I/O3 /CS D0 DM DQS I/O0 I/O1 I/O2 I/O3 /CS D1 DM DQS I/O0 I/O1 I/O2 I/O3 /CS D2 DM DQS I/O0 I/O1 I/O2 I/O3 /CS D3 DM DQS I/O0 I/O1 I/O2 I/O3 /CS D4 DM DQS I/O0 I/O1 I/O2 I/O3 /CS D5 DM DQS I/O0 I/O1 I/O2 I/O3 /CS D6 DM DQS I/O0 I/O1 I/O2 I/O3 /CS D7 DM DQS I/O0 I/O1 I/O2 I/O3 /CS D8 DM DM0/DQS9 DQ4 DQ5 DQ6 DQ7 DM1/DQS10 DQ12 DQ13 DQ14 DQ15 DM2/DQS11 DQ20 DQ21 DQ22 DQ23 DM3/DQS12 DQ28 DQ29 DQ30 DQ31 DM4/DQS13 DQ36 DQ37 DQ38 DQ39 DM5/DQS14 DQ44 DQ45 DQ46 DQ47 DM6/DQS15 DQ52 DQ53 DQ54 DQ55 DM7/DQS16 DQ60 DQ61 DQ62 DQ63 DM8/DQS17 CB4 CB5 CB6 CB7 DQS I/O0 I/O1 I/O2 I/O3 /CS DD09 DM DQS I/O0 I/O1 I/O2 I/O3 /CS DM DD010 DQS I/O0 I/O1 I/O2 I/O3 /CS DM DD011 DQS I/O0 I/O1 I/O2 I/O3 /CS DM DD012 DQS I/O0 I/O1 I/O2 I/O3 /CS DM DD013 DQS I/O0 I/O1 I/O2 I/O3 /CS DM DD014 DQS I/O0 I/O1 I/O2 I/O3 /CS DM DD015 DQS I/O0 I/O1 I/O2 I/O3 /CS DM DD016 DQS I/O0 I/O1 I/O2 I/O3 /CS DM DD017 VDDSPD VDDQ VDD VREF VSS VDDID Serial PD DO-D8 DO-D8 DO-D8 DO-D8 Strap:see Note 4 Serial PD SCL SDA WP A0 A1 A2 SA0 SA1SA2 /S0 R /RS->/CS : SDRAMs D0-D17 BA0-BA1 E RBA0-RBA1-> : BA0->BA1 : SDRAMs D0-D17 A0-A13 /RAS /CAS CKE /WE G RA0-RA13-> : A0->A13 : SDRAMs D0-D17 I /RRAS->/RAS : SDRAMs D0-D17 S T /RCAS->/CAS : SDRAMs D0-D17 E R RCKEA->CKE : SDRAMs D0-D17 /RWE->WE : SDRAMs D0-D17 Note : 1. DQ-to-I/O wiring may be changed within a byte. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. PCK /PCK /RESET 3. DQ/DQS resistors should be 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ) : CKO, /CKO------PLL* * Wire per Clock Loading Table/Wiring Diagram STRAP OUT (OPEN) : VDD = VDDQ STRAP IN (VSS) : VDD ≠ VDDQ 5. Address and control resistors should be 22 Ohms. Rev. 1.1 /May. 2005 5 Free Datasheet http://www.datasheet4u.com/ 5 Page 184pin Registered DDR SDRAM DIMMs AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V) Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF + 0.31 - 0.7 0.5VDDQ-0.2 Max - VREF - 0.31 VDDQ + 0.6 0.5VDDQ+0.2 Unit V V V V Note 1 2 Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same. AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V) Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns Ω Ω pF OUTPUT LOAD CIRCUIT Output VTT RT=50Ω Zo=50Ω CL=30pF VREF Rev. 1.1 /May. 2005 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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