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PDF NVT2004 Data sheet ( Hoja de datos )

Número de pieza NVT2004
Descripción (NVT2003 - NVT2006) Bidirectional voltage-level translator
Fabricantes NXP Semiconductors 
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NVT2003/04/06
Bidirectional voltage-level translator for open-drain and
push-pull applications
Rev. 4 — 7 September 2012
Product data sheet
1. General description
The NVT2003/04/06 is a family of bidirectional voltage level translators operational from
1.0 V to 3.6 V (Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage
translations between 1.0 V and 5 V without the need for a direction pin in open-drain or
push-pull applications. Bit widths ranging from 3-bit to 6-bit are offered for level translation
application with transmission speeds < 33 MHz for an open-drain system with a 50 pF
capacitance and a pull-up of 197 .
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by Vref(B). To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2. Features and benefits
Provides bidirectional voltage translation with no direction pin
Less than 1.5 ns maximum propagation delay
Allows voltage level translation between:
1.0 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.2 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
1.8 V Vref(A) and 3.3 V or 5 V Vref(B)
2.5 V Vref(A) and 5 V Vref(B)
3.3 V Vref(A) and 5 V Vref(B)
Free Datasheet http://www.datasheet4u.com/

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NVT2004 pdf
NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
5.2 Pin description
Table 2.
Symbol
GND
VREFA
A1
A2
A3
A4
A5
A6
B1
B2
B3
B4
B5
B6
VREFB
EN
Pin description
Pin
NVT2003DP[1] NVT2004TL[2]
11
22
33
44
55
-6
--
--
8 10
79
68
-7
--
--
9 11
10 12
NVT2006BQ,
NVT2006PW[3]
1
2
3
4
5
6
7
8
14
13
12
11
10
9
15
16
NVT2006BS[3]
15
16
1
2
3
4
5
6
12
11
10
9
8
7
13
14
Description
ground (0 V)
low-voltage side reference
supply voltage for An
low-voltage side; connect to VREFA
through a pull-up resistor
high-voltage side; connect to VREFB
through a pull-up resistor
high-voltage side reference
supply voltage for Bn
switch enable input; connect to VREFB
and pull-up through a high resistor
[1] 3-bit NVT2003 available in TSSOP10 package.
[2] 4-bit NVT2004 available in HXSON12 package.
[3] 6-bit NVT2006 available in TSSOP16, DHVQFN16, HVQFN16 packages.
NVT2003_04_06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 September 2012
© NXP B.V. 2012. All rights reserved.
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NVT2004 arduino
NXP Semiconductors
NVT2003/04/06
Bidirectional voltage-level translator
7.4.1.1 Example maximum frequency
Question — We need to make the PLL area of a new line card backwards compatible and
need to convert one GTL signal to LVTTL, invert it, and convert it back to GTL. The signal
we want to convert is random in nature but will mostly be around 19 MHz with very long
periods of inactivity where either a HIGH or LOW state will be maintained. The traces are
1 or 2 inches long with trace capacitance of about 2 pF per inch.
Answer — The frequency of the NVT20xx is limited by the capacitance of the part, the
capacitance of the traces and the pull-up resistors used. The limiting case is probably the
LOW-to-HIGH transition in the GTL to LVTTL direction, and there the use of the lowest
acceptable resistor values will minimize the rise time delay. Assuming 50 pF capacitance
and 220 resistance, the RC time constant is 11 ns (50 pF 220 ). With 19 MHz
corresponding to 50 ns period the NVT20xx will support this application.
8. Limiting values
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Symbol Parameter
Conditions
Min
Vref(A)
Vref(B)
VI
VI/O
reference voltage (A)
reference voltage (B)
input voltage
voltage on an input/output pin
0.5
0.5
0.5[1]
0.5[1]
Ich channel current (DC)
IIK input clamping current
IOK output clamping current
Tstg storage temperature
VI < 0 V
-
50
[2] 50
65
Max
+6
+6
+6
+6
128
-
+50
+150
Unit
V
V
V
V
mA
mA
mA
C
[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp
current ratings are observed.
[2] Low duty cycle pulses, not DC because of heating.
9. Recommended operating conditions
Table 7.
Symbol
VI/O
Vref(A)
Vref(B)
VI(EN)
Isw(pass)
Tamb
Operating conditions
Parameter
voltage on an input/output pin
reference voltage (A)
reference voltage (B)
input voltage on pin EN
pass switch current
ambient temperature
Conditions
An, Bn
VREFA
VREFB
operating in free-air
[1] Vref(A) Vref(B) 1 V for best results in level shifting applications.
Min
0
[1] 0
[1] 0
0
-
40
Max Unit
5.5 V
5.4 V
5.5 V
5.5 V
64 mA
+85 C
NVT2003_04_06
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 7 September 2012
© NXP B.V. 2012. All rights reserved.
11 of 27
Free Datasheet http://www.datasheet4u.com/

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