HMP125F7EFR8C-S6D5 Datasheet PDF - Hynix
| Part Number | HMP125F7EFR8C-S6D5 | |
| Description | 240pin Fully Buffered DDR2 SDRAM DIMMs | |
| Manufacturers | Hynix | |
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240pin Fully Buffered DDR2 SDRAM DIMMs based on 1Gb E-ver.
This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow
host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that
isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of
each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the
host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host
controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point
Link Interface at 1.5V power.
The AMB also allows buffering of memory traffic to support large memory capacities. All memory control
for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access and power management. The AMB interface is responsible for
handling channel and memory requests to and from the local FBDIMM and for forwarding request to other
FBDIMMs on the memory channel.
FEATURES
• 240 pin Fully Buffered ECC Dual-In-Line DDR2 SDRAM Module
• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 interface
• Built with 1Gb DDR2 SDRAMs in 60ball FBGA
• Host interface and AMB component industry standard compliant
• MBIST, IBIST test functions
• 8 Bank architecture
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• 133.35 x 30.35 mm form factor
• RoHS compliant
• Full DIMM Heat Spreader
This document is a general product description and is subject to change without notice. Hynix Electronics does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.2 / Sep. 2008
1
Free Datasheet http://www.datasheet4u.com/
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1240pin Fully Buffered DDR2 SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
1GB(128Mbx72) ECC FB-DIMM
/S0
DQS0
/DQS0
DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D0
DQS /DQS
DQS1
/DQS1
DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D1
DQS /DQS
DQS2
/DQS2
DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D2
DQS /DQS
DQS3
/DQS3
DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D3
DQS /DQS
All address/command/control/clock
VTT
Serial PD
SCL
SCL U0
SDA
WP A0 A1 A2
SA0 SA1 SA2
SDA
VTT
VCC
VDD SPD
VDD
VREF
VSS
DQS4
/DQS4
DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D4
DQS /DQS
DQS5
/DQS5
DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D5
DQS /DQS
DQS6
/DQS6
DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D6
DQS /DQS
DQS7
/DQS7
DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D7
DQS /DQS
DQS8
/DQS8
DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NU /CS
/RDQS
D8
DQS /DQS
PN0-PN13
SN0-SN13
/PN0-/PN13
/SN0-/SN13
Terminators
AMB
Serial PD,AMB
PS0-PS9
SS0-SS9
/PS0-/PS9
A /SS0-/SS9
DQ0-DQ63
CB0-CB7
M
B
/S0-/CS(all SDRAMs)
CKE0 -> CKE
DQS0-DQS17
DO-D8, AMB
/DQS0-/DQS8
ODT -> ODT
DO-D8
SCL
SDA
BA0-BA2
SA0-SA2
A0-A15
DO-D8,SPD, AMB
/RESET
/RAS
/CAS
/WE
SCK/ /SCK
CK/ /CK
Notes :
1. DQ-to-I/O wiring may be changed within a byte.
2. There are two physical copies of each address/command/control/clock.
Rev. 0.2 / Sep. 2008
5
Free Datasheet http://www.datasheet4u.com/
Preview 5 Page |
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