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PDF HIP6304 Data sheet ( Hoja de datos )
| Número de pieza | HIP6304 | |
| Descripción | Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller | |
| Fabricantes | Intersil Corporation | |
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TM
Data Sheet
HIP6304
March 2000
File Number 4840
Microprocessor CORE Voltage Regulator
Multi-Phase Buck PWM Controller
The HIP6304 multi-phase PWM control IC together with its
companion gate drivers, the HIP6601, HIP6602 or HIP6603
and Intersil MOSFETs provides a precision voltage
regulation system for advanced microprocessors.
Multiphase power conversion is a marked departure from
earlier single phase converter configurations previously
employed to satisfy the ever increasing current demands of
modern microprocessors. Multi-phase convertors, by
distributing the power and load current results in smaller and
lower cost transistors with fewer input and output capacitors.
These reductions accrue from the higher effective
conversion frequency with higher frequency ripple current
due to the phase interleaving process of this topology. For
example, a two phase convertor operating at 350kHz will
have a ripple frequency of 700kHz. Moreover, greater
convertor bandwidth of this design results in faster response
to load transients.
Outstanding features of this controller IC include
programmable VID codes from the microprocessor that
range from 1.30V to 2.05V with a system accuracy of ±1%.
Pull up currents on these VID pins eliminates the need for
external pull up resistors. In addition “droop” compensation,
used to reduce the overshoot or undershoot of the CORE
voltage, is easily programmed with a single resistor.
Another feature of this controller IC is the PGOOD monitor
circuit which is held low until the CORE voltage increases,
during its Soft-Start sequence, to within 10% of the
programmed voltage. Over-voltage, 15% above programmed
CORE voltage, results in the converter shutting down and
turning the lower MOSFETs ON to clamp and protect the
microprocessor. Under voltage is also detected and results
in PGOOD low if the CORE voltage falls 10% below the
programmed level. Over-current protection reduces the
regulator current to less than 25% of the programmed trip
value. These features provide monitoring and protection for
the microprocessor and power system.
Features
• AMD Athlon Compatible Multi-Phase Power Conversion
• Precision Channel Current Sharing
- Loss Less Current Sampling - Uses rDS(ON)
• Precision CORE Voltage Regulation
- ±1% System Accuracy Over Temperature
• Microprocessor Voltage Identification Input
- 4-Bit VID Input
- 1.30V to 2.05V in 50mV Steps
- Programmable “Droop” Voltage
• Fast Transient Recovery Time
• Over Current Protection
• High Ripple Frequency, (Channel Frequency) Times
Number Channels . . . . . . . . . . . . . . . . . 100kHz to 3MHz
Ordering Information
PART NUMBER TEMP. (oC) PACKAGE PKG. NO.
HIP6304CB
0 to 70 16 Ld SOIC M16.15
HIP6304CB-T
16 Ld SOIC Tape and Reel
HIP6304EVAL1
Evaluation Platform
Pinout
HIP6304 (SOIC)
TOP VIEW
VID3 1
VID2 2
VID1 3
VID0 4
EN 5
COMP 6
FB 7
FS/DIS 8
16 VCC
15 PGOOD
14 ISEN1
13 PWM1
12 PWM2
11 ISEN2
10 VSEN
9 GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Athlon™ is a trademark of Advanced Micro Devices, Inc.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
1 page  
HIP6304
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class TBD
Recommended Operating Conditions
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
106
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
INPUT SUPPLY POWER
Input Supply Current
POR (Power-On Reset) Threshold
REFERENCE AND DAC
RT = 100kΩ, Active and Disabled Maximum Limit
VCC Rising
VCC Falling
-
4.25
3.75
System Accuracy
Percent system deviation from programmed VID Codes
-1
DAC (VID0 - VID3) Input Low Voltage
DAC Programming Input Low Threshold Voltage
-
DAC (VID0 - VID3) Input High Voltage
DAC Programming Input High Threshold Voltage
2.0
VID Pull-Up
VIDx = 0V or VIDx = 3V
10
CHANNEL GENERATOR
Frequency, FSW
Adjustment Range
RT = 100kΩ, ±1%
See Figure 10
245
0.05
Disable Voltage
ERROR AMPLIFIER
Maximum voltage at FS/DIS to disable controller. IFS/DIS = 1mA.
-
DC Gain
Gain-Bandwidth Product
Slew Rate
Maximum Output Voltage
Minimum Output Voltage
ISEN
Full Scale Input Current
RL = 10K to Ground
CL = 100pF, RL = 10K to Ground
CL = 100pF, Load = ±400µA
RL = 10K to ground, Load = 400µA
RL = 10K to ground, Load = -400µA
-
-
-
3.6
-
-
Over-Current Trip Level
-
POWER GOOD MONITOR
Under-Voltage Threshold
VSEN Rising
-
Under-Voltage Threshold
VSEN Falling
-
PGOOD Low Output Voltage
PROTECTION
IPGOOD = 4mA
-
Over-Voltage Threshold
VSEN Rising
1.12
Percent Over-Voltage Hysteresis
VSEN Falling after Over-Voltage
-
TYP
10
4.38
3.88
-
-
-
20
275
-
-
72
18
5.3
4.1
0.16
50
82.5
0.92
0.90
0.18
1.15
2
MAX UNITS
15 mA
4.5 V
4.00 V
1%
0.8 V
-V
40 µA
305 kHz
1.5 MHz
1.0 V
- dB
- MHz
- V/µs
-V
0.5 V
- µA
- µA
- VDAC
- VDAC
0.4 V
1.2 VDAC
-%
5
5 Page 
HIP6304
Example: Using the previously given conditions, and
For ILT = 50A,
n =2
Then ISAMPLE = 25.49A
As discussed previously, the voltage drop across each Q2
transistor at the point in time when current is sampled is
rDSON (Q2) x ISAMPLE. The voltage at Q2’s drain, the
PHASE node, is applied through the RISEN resistor to the
HIP6304 ISEN pin. This pin is held at virtual ground, so the
current into ISEN is:
ISENSE = ISAMPLE x rDS(ON) (Q2) / RISEN.
RIsen = ISAMPLE x rDS(ON) (Q2) / 50µA
Example: From the previous conditions,
where ILT
= 50A,
ISAMPLE
= 25.49A,
rDS(ON) (Q2) = 4mΩ
Then: RISEN = 2.04K and
ICURRENT TRIP = 165%
Short circuit ILT = 82.5A.
Channel Frequency Oscillator
The channel oscillator frequency is set by placing a resistor,
RT, to ground from the FS/DIS pin. Figure 10 is a curve
showing the relationship between frequency, FSW, and
resistor RT. To avoid pickup by the FS/DIS pin, it is important
to place this resistor next to the pin. If this pin is also used to
disable the converter, it is also important to locate the pull-
down device next to this pin.
1,000
500
200
100
50
20
10
5
2
1
10 20
50 100 200 500 1,000 2,000 5,000 10,000
CHANNEL OSCILLATOR FREQUENCY, FSW (kHz)
FIGURE 10. RESISTANCE RT vs FREQUENCY
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
causes voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit
and lead to device over-voltage stress. Careful component
layout and printed circuit design minimizes the voltage
spikes in the converter. Consider, as an example, the turnoff
transition of the upper PWM MOSFET. Prior to turnoff, the
upper MOSFET was carrying channel current. During the
turnoff, current stops flowing in the upper MOSFET and is
picked up by the lower MOSFET. Any inductance in the
switched current path generates a large voltage spike during
the switching interval. Careful component selection, tight
layout of the critical components, and short, wide circuit
traces minimize the magnitude of voltage spikes. Contact
Intersil for evaluation board drawings of the component
placement and printed circuit board.
There are two sets of critical components in a DC-DC
converter using a HIP6304 controller and a HIP6601 gate
driver. The power components are the most critical because
they switch large amounts of energy. Next are small signal
components that connect to sensitive nodes or supply
critical bypassing current and signal coupling.
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, CIN,
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate the gate driver close to the MOSFETs.
The critical small components include the bypass capacitors
for VCC and PVCC on the gate driver ICs. Locate the
bypass capacitor, CBP, for the HIP6304 controller close to
the device. It is especially important to locate the resistors
associated with the input to the amplifiers close to their
respective pins, since they represent the input to feedback
amplifiers. Resistor RT, that sets the oscillator frequency
should also be located next to the associated pin. It is
especially important to place the RSEN resistor(s) at the
respective terminals of the HIP6304.
A multi-layer printed circuit board is recommended. Figure 11
shows the connections of the critical components for one
output channel of the converter. Note that capacitors CIN and
COUT could each represent numerous physical capacitors.
Dedicate one solid layer, usually the middle layer of the PC
board, for a ground plane and make all critical component
ground connections with vias to this layer. Dedicate another
solid layer as a power plane and break this plane into smaller
islands of common voltage levels. Keep the metal runs from
the PHASE terminal to inductor LO1 short. The power plane
should support the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers for
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HIP6304.PDF ] | |
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