|
|
PDF HIP5061 Data sheet ( Hoja de datos )
| Número de pieza | HIP5061 | |
| Descripción | 7A/ High Efficiency Current Mode Controlled PWM Regulator | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HIP5061 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
HIP5061
April 1994
Features
• Single Chip Current Mode Control IC
• 60V, On-Chip DMOS Power Transistor
• Thermal Protection
• Over-Current Protection
• 250kHz Operation
• Output Rise and Fall Times - 10ns
• On-Chip Reference Voltage - 5.1V
• Slope Compensation
• VDD Clamp Allows 10.8V to 60V Supply
• Supply Current Does Not Increase When Power
Device is On
Applications
• Distributed / Board Mounted Power Supplies
• DC - DC Converter Modules
• Voltage Inverters
• Small Uninterruptable Power Supplies
• Cascode Switching for Off Line SMPS
7A, High Efficiency Current
Mode Controlled PWM Regulator
Description
The HIP5061 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog circuitry on the same Intelligent Power IC. The
standard “Boost”, “Buck-Boost”, “Cuk”, “Forward”, “Flyback”
and the “SEPIC” (Single-Ended Primary Inductance Con-
verter) power supply topologies may be implemented with
this single control IC.
Over-temperature and rapid short-circuit recovery circuitry is
incorporated within the IC. These protection circuits disable
the drive to the power transistor to protect the transistor and
insure rapid restarting of the supply after the short circuit is
removed.
As a result of the power DMOS transistors current (7A at 30%
duty cycle, 5A DC) and 60V capability, supplies with output
power over 50W are possible.
Ordering Information
PART TEMPERATURE
NUMBER
RANGE
PACKAGE
HIP5061DS 0oC to +85oC 7 Lead Staggered “Gullwing” SIP
Pinout
HIP5061 (SIP)
TOP VIEW
Simplified Functional Diagram
VIN
SOURCE
(TAB)
PIN 7 VDD
PIN 6 VG
PIN 5 DRAIN
PIN 4 SOURCE
PIN 3 FB
PIN 2 VC
PIN 1 GND
DO NOT
USE
HIP5061
CLOCK
OVER
TEMP
VDD
VDD CLAMP
CONTROL
LOGIC
VG
GATE
DRIVER
V/I
DRAIN
SOURCE
(TAB)
AMP
VC
FB
UNDER
VOLTAGE
SLOPE
COMPENSATION
2.5V
5.1V
REFERENCE
GND
VOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
407-727-9207 | Copyright © Intersil Corporation 1999
7-53
File Number 3390.2
1 page  
HIP5061
MaxCI, Maximum Controllable Current - The peak current
for the DMOS transistor when the Voltage-to-Current Con-
verter is at its full scale output. The DMOS transistor current
may exceed this value during the blanking time so proper
precautions should be taken. This parameter is unchanged
for the first 3/8 of the cycle and then decreases linearly with
time because of the Current Ramp becoming active.
Current Compensation Ramp
∆I/∆t, Compensation Ramp Rate - At a given voltage on VC
the DMOS transistor will turn off at some current that stays
constant for about the first 1.5µs of the cycle. After 1.5µs, the
turnoff current starts to linearly decrease. This parameter
specifies the change in the DMOS transistor turnoff current.
tRD, Compensation Ramp Delay - The time into each cycle
that the compensation ramp turns on. The Current Compen-
sation Ramp, used for Slope Compensation, is developed by
the Current Ramp block shown in the FUNCTIONAL BLOCK
DIAGRAM of Figure 2.
Start-Up
VDDMIN, Rising VDD Threshold Voltage - The minimum
voltage on VDD needed to enable the IC.
VDDHYS, Power - On Hysteresis Voltage - The difference
between the voltage on VDD that enables the IC and the volt-
age that disables the IC.
VCEN, Enable Comparator Threshold Voltage - The mini-
mum voltage on VC needed to enable the IC. The IC can be
shutdown from an open-collector logic gate by pulling down
the VC pin to GND.
RVC, Power - Up Resistance - When VDD is below VDDMIN,
the NMOS transistor connected to the VC pin is turned on to
make sure the VC node is low. Thus the voltage on VC can
gradually build up as will the trip current on the DMOS tran-
sistor. This is the only form of “soft start” included on the IC.
The resistance is measured between the VC and GND pins.
Thermal Monitor
TJ , Rising Temperature Threshold - The IC temperature
that causes the IC to disable itself so as to prevent damage.
Proper heat-sinking is required to avoid over-temperature
conditions, especially during start-up when the DMOS tran-
sistor may stay on for a long time if an external soft-start cir-
cuit is not added.
TJHY, Temperature Hysteresis - The IC must cool down
this much after it is disabled by being too hot before it can
resume normal operation.
VDD
7
VDD
CLAMP
VG
6
GND
1
VC
2
FB
3
RAMP ENABLE
RAMP RESET
BAND GAP
REFERENCE
REGULATOR
BIAS
CIRCUITS
VDD
CURRENT
RAMP
- VREF = 5.1V
+
10.3V
VDD MONITOR
CLOCK
CONTROL
LOGIC
GATE
DRIVER
ERROR
AMP
DISABLE
-
ERROR
AMP
+
2KΩ
5.1V
VREF
2KΩ
+
UNDER VOLTAGE
LOCK OUT
ENABLE
-
ENABLE
1.5V
THERMAL
VDD
VOLTAGE TO
CURRENT
MONITOR
+ CONVERTER
360Ω
-
CURRENT
ERROR CURRENT
COMPARE
-
360Ω
+
LIGHT LOAD
COMPARATOR
+
SHORT
CIRCUIT
HIP5061
-
7.0V
100ns
BLANKING CURRENT
MONITORING
CURRENT SAMPLE
INTERNAL LEAD
INDUCTANCE
AND RESISTANCE
DRAIN
5
TAB
SOURCE
SOURCE
4
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF THE HIP5061
7-57
5 Page 
HIP5061
Typical Performance Curves (Continued)
180
175 VDD = VG = 12V
170
165
160
155
150
145
140
0
10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (oC)
FIGURE 27. TYPICAL MINIMUM DMOS TRANSISTOR “ON”
TIME vs TEMPERATURE
150
145 VDD = VG = 12V
140
135
130
125
120
115
0 10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (oC)
FIGURE 28. TYPICAL MINIMUM DMOS TRANSISTOR “OFF”
TIME vs TEMPERATURE
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5 VDD = VG = 12V, DUTY CYCLE = 96%
4.0
0
10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (oC)
FIGURE 29. TYPICAL MAXIMUM CONTROLLABLE PEAK
DMOS DRAIN CURRENT vs TEMPERATURE
-0.50
-0.55
-0.60
VDD = VG = 12V
-0.65
-0.70
-0.75
-0.80
-0.85
-0.90
-0.95
-1.00
0
10 20 30 40 50 60 70 80
AMBIENT TEMPERATURE (oC)
FIGURE 30. TYPICAL COMPENSATING RAMP RATE
vs TEMPERATURE
90 100
1.80
1.75
1.70
VDD = VG = 12V
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
0 10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (oC)
FIGURE 31. TYPICAL COMPENSATION RAMP DELAY
TIME vs TEMPERATURE
11
10 VDDMIN
9
8
7
6
5 VFB = 4V
4
3
2
1 VDDHYS
0
0 10 20 30 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (oC)
FIGURE 32. TYPICAL RISING VDD COMPARATOR THRESHOLD
VOLTAGE vs TEMPERATURE
7-63
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet HIP5061.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HIP5060 | Power Control IC Single Chip PowerSupply | Intersil Corporation |
| HIP5061 | 7A/ High Efficiency Current Mode Controlled PWM Regulator | Intersil Corporation |
| HIP5061DS | 7A/ High Efficiency Current Mode Controlled PWM Regulator | Intersil Corporation |
| HIP5062 | Power Control IC Single Chip Dual Switching Power Supply | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |