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PDF HIP4081 Data sheet ( Hoja de datos )
| Número de pieza | HIP4081 | |
| Descripción | 80V/2.5A Peak/ High Frequency Full Bridge FET Driver | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HIP4081
November 1996
80V/2.5A Peak, High Frequency
Full Bridge FET Driver
Features
• Independently Drives 4 N-Channel FET in Half Bridge
or Full Bridge Configurations
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load at 1MHz in Free Air at 50oC with
Rise and Fall Times of Typically 10ns
• User-Programmable Dead Time
• On-Chip Charge-Pump and Bootstrap Upper Bias
Supplies
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V
Logic Levels
• Very Low Power Consumption
Applications
• Medium/Large Voice Coil Motors
• Full Bridge Power Supplies
• Class D Audio Power Amplifiers
• High Performance Motor Controls
• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals
• U.P.S.
Ordering Information
PART
NUMBER
HIP4081IP
HIP4081IB
TEMP.
RANGE (oC)
PACKAGE
-40 to 85 20 Lead Plastic DIP
-40 to 85 20 Lead Plastic SOIC
PKG.
NUMBER
E20.3
M20.3
Description
The HIP4081 is a high frequency, medium voltage Full
Bridge N-Channel FET driver IC, available in 20 lead plastic
SOIC and DIP packages. The HIP4081 can drive every pos-
sible switch combination except those which would cause a
shoot-through condition. The HIP4081 can switch at fre-
quencies up to 1MHz andssssss is well suited to driving
Voice Coil Motors, high-frequency Class D audio amplifiers,
and power supplies.
For example, the HIP4081 can drive medium voltage brush
motors, and two HIP4081s can be used to drive high perfor-
mance stepper motors, since the short minimum “on-time”
can provide fine micro-stepping capability.
Short propagation delays of approximately 55ns maximizes
control loop crossover frequencies and dead-times which
can be adjusted to near zero to minimize distortion, resulting
in rapid, precise control of the driven load.
A similar part, the HIP4080, includes an on-chip input com-
parator to create a PWM signal from an external triangle
wave and to facilitate “hysteresis mode” switching.
See Application Note AN9325 for HIP4081, Intersil Answer-
FAX, (407) 724-7800, document #99325. Intersil web home
page: http://www.semi.intersil.com
Similar part HIP4081A includes undervoltage circuitry which
does not require the circuitry shown in Figure 30 of this data
sheet.
Pinout
HIP4081
(PDIP, SOIC)
TOP VIEW
BHB 1
BHI 2
DIS 3
VSS 4
BLI 5
ALI 6
AHI 7
HDEL 8
LDEL 9
AHB 10
20 BHO
19 BHS
18 BLO
17 BLS
16 VDD
15 VCC
14 ALS
13 ALO
12 AHS
11 AHO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 3556.7
1 page  
HIP4081
Electrical Specifications VanDdDT=AV=C2C5o=CV,AUHnBle=ssVOBHthBer=w1is2eV,SVpSeScifi=eVdAL(SCo=nVtBinLuSe=d)VAHS = VBHS = 0V, RHDEL = RLDEL = 100K
PARAMETER
SYMBOL
TEST CONDITIONS
TJ = 25oC
TJS = -40oC
TO 125oC
MIN TYP MAX MIN MAX UNITS
Peak Pullup Current
Peak Pulldown Current
IO+ VOUT = 0V
IO- VOUT = 12V
1.7 2.6 3.8 1.4 4.1
1.7 2.4 3.3 1.3 3.6
A
A
Switching Specifications
PARAMETER
VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V, RHDEL = RLDEL = 10K,
CL = 1000pF
TJ = +25oC
TJS = 40oC
TO 125oC
SYMBOL
TEST CONDITIONS MIN TYP MAX MIN MAX UNITS
Lower Turn-off Propagation Delay
(ALI-ALO, BLI-BLO)
TLPHL
- 30 60 - 80 ns
Upper Turn-off Propagation Delay
(AHI-AHO, BHI-BHO)
THPHL
- 35 70 - 90 ns
Lower Turn-on Propagation Delay
(ALI-ALO, BLI-BLO)
TLPLH
- 45 70 - 90 ns
Upper Turn-on Propagation Delay
(AHI-AHO, BHI-BHO)
THPLH
- 60 90 - 110 ns
Rise Time
Fall Time
Turn-on Input Pulse Width
Turn-off Input Pulse Width
Disable Turn-off Propagation Delay
(DIS - Lower Outputs)
TR
TF
TPWIN-ON
TPWIN-OFF
TDISLOW
- 10 25 - 35 ns
- 10 25 - 35 ns
50 -
- 50 -
ns
40 -
- 40 -
ns
- 45 75 - 95 ns
Disable Turn-off Propagation Delay
(DIS - Upper Outputs)
TDISHIGH
- 55 85 - 105 ns
Disable to Lower Turn-on Propagation Delay
(DIS - ALO and BLO)
TDLPLH
- 35 70 - 90 ns
Refresh Pulse Width (ALO and BLO)
Disable to Upper Enable (DIS - AHO and BHO)
TREF-PW
THEN
160 260 380 140 420
- 335 500 - 550
ns
ns
INPUT
ALI, BLI
AHI, BHI
XX
1X
01
00
NOTE: X signifies that input can be either a “1” or “0”.
TRUTH TABLE
DIS
1
0
0
0
ALO, BLO
0
1
0
0
OUTPUT
AHO, BHO
0
0
1
0
5
5 Page 
HIP4081
Typical Performance Curves VDD = VCC = VAHB = VBHB = 12V, VSS = VALS = VBLS = VAHS = VBHS = 0V,
RHDEL = RLDEL = 100K and TA = 25oC, Unless Otherwise Specified (Continued)
6.0 1500
1250
5.5
1000
5.0
4.5
4.0
-40
-20
0 20 40 60 80 100
JUNCTION TEMPERATURE (oC)
120
FIGURE 22. VLDEL, VHDEL VOLTAGE vs TEMPERATURE
750
500
250
0
6
-40oC
0oC
25oC
75oC
125oC
8 10 12
BIAS SUPPLY VOLTAGE (V)
14
FIGURE 23. HIGH LEVEL OUTPUT VOLTAGE VCC - VOH vs
BIAS SUPPLY AND TEMPERATURE AT 100mA
1500
1250
1000
-40oC
0oC
750
500
250
0
6
25oC
75oC
125oC
8 10 12
BIAS SUPPLY VOLTAGE (V)
14
FIGURE 24. LOW LEVEL OUTPUT VOLTAGE VOL vs BIAS
SUPPLY AND TEMPERTURE AT 100mA
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6 7 8 9 10 11 12 13 14 15 16
VDD, VCC, VAHB, VBHB (V)
FIGURE 25. PEAK PULLDOWN CURRENT IO vs BIAS SUPPLY
VOLTAGE
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6 7 8 9 10 11 12 13 14 15 16
VDD, VCC, VAHB, VBHB (V)
FIGURE 26. PEAK PULLUP CURRENT IO+ vs BIAS SUPPLY
VOLTAGE
500
200 10,000pF
100 3,000pF
50 1,000pF
20 100pF
10
5
2
1
0.5
0.2
0.1
1
2
5 10 20
50 100 200
SWITCHING FREQUENCY (kHz)
500 1000
FIGURE 27. LOW VOLTAGE BIAS CURRENT IDD (LESS
QUIESCENT COMPONENT) vs FREQUENCY AND
GATE LOAD CAPACITANCE
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet HIP4081.PDF ] | |
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