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PDF HIP0063AB Data sheet ( Hoja de datos )

Número de pieza HIP0063AB
Descripción Hex Low Side MOSFET Driver with Serial or Parallel Interface and Diagnostic Fault Control
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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HIP0063
PRELIMINARY
October 1995
Hex Low Side MOSFET Driver with Serial or
Parallel Interface and Diagnostic Fault Control
Features
• Six Channel MOSFET Driver with Gate Drive
Control by Serial (SPI) or Parallel Interface and
an Option for PWM Logic Switching Control
• Drain Monitor Provides Fault Detection and
Voltage Clamp for Each Channel
• Output Voltage Zener Clamp. . . . . . . . . . 67V Typ
• 5V CMOS Logic Level Input Control
• VCC Logic Level Power Supply
- 5V VCC Logic Power Supply
- Turns Off Gate Drive for Low or Loss of VCC
• VPWR System Level Power Supply Management
- 5.5V to 17V Battery/System Level Power
Supply Monitor
- Over-Voltage Shutdown . . . . . . . . . . . . 35V Typ
• Output Supply/Load Short and Open
Load/Ground Short Fault Detection
• Automatic Change to Low Duty Cycle Drive
Mode When Output Short-to-Supply Detected
• Fault Diagnostic Feedback via the SPI Bus
• Operating Temp Range . . . . . . . -40oC to +125oC
Applications
• Automotive and Industrial Systems
• Control of Solenoids, Relays and Lamp Drivers
• Interface to Logic and µP Controllers
• Robotic System Controller
Description
The HIP0063 is a logic controlled, six channel Low Side Power Driver. As
shown in the Block Diagram, the outputs are controlled via the serial data
interface or, by user option, each output may be independently controlled
from the respective parallel input. In addition, PWM logic switching control
(HLOS) may be directly applied to channels 0 and 1 in parallel, or channels 4
and 5 in parallel.
Output fault conditions may be detected as an output load short to supply
when the output is ON or as an open load/ground short when the output is
OFF. If an over-current short exists at one output, gate drive goes to a low
duty cycle mode. It will remain in the low duty cycle mode until switched off or
the fault is cleared. Fault bits are sent to a fault register to indicate which
channel is at fault. The fault bits are indicated by a logic one and is internally
latched when CS goes low. A fault bit will return to zero when the fault disap-
pears. Either an 8-bit or 16-bit SPI communication mode may be used. Refer
to the application section for bit control information.
Over-voltage shutdown protection for all outputs will occur when VPWR (Battery/
MOSFET Supply) exceeds 35V typical. When VCC is less than 3.5V, gate drive
is switched off. The input and gate control logic is fully function when the VCC
supply is greater than 4V typical. The HIP0063 has an internal drain-to-gate
zener which is used to voltage clamp the output drain-to-source voltage of the
MOSFET.
The HIP0063 is fabricated in a Power BiMOS IC process, and is intended for
use in automotive and other applications having a wide range of temperature
and electrical stress conditions. It is particularly well suited for MOSFET con-
trol in circuits driving lamps, displays, relays, and solenoids in applications
requiring low operating power.
Ordering Information
PART
NUMBER
HIP0063AB
TEMPERATURE
RANGE
-40oC to +125oC
PACKAGE
28 Lead Plastic SOIC (W)
Pinout
HIP0063 SOIC
TOP VIEW
HLOS 1
HPW01 2
HPW45 3
P10 4
P11 5
P12 6
P13 7
P14 8
P15 9
CS 10
SO 11
SI 12
SCK 13
GND 14
28 VPWR
27 G0
26 D0
25 G1
24 D1
23 D2
22 G2
21 G3
20 D3
19 D4
18 G4
17 D5
16 G5
15 VCC
Block Diagram
+VPWR
VPWR
VCC
HPW01
HPW45
HLOS
CS
SI
SO
SCK
PI0-5
OVSD
CHANNEL#0 - (1 OF 6) FAULT LOGIC
+5V
F0 AND LATCH
FAULT DATA
POR
OVSD
MUX
PWM
CONTROL
S0
S6 P0
SPI (SER.)
CONTROL
S0-5
F0-5
PI0-5
(6)
TG
GATE
CONTROL
LOGIC
TG
POR
HIP0063
OSC AND
TIME DELAY
CONTROL
D0
(DRAIN
MONITOR
VOLT,VDM)
G0
(GATE DR.
VOLT.,VG)
GND
EXT POWER
MOSFET AND
TYP LOAD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
File Number 4009

1 page




HIP0063AB pdf
Specifications HIP0063
Serial Peripheral Interface Timing (See Figure 4)
PARAMETERS
SYMBOL
TEST CONDITION
Clock Operating Frequency
Clock Period
Clock High Time
Clock Low Time
Falling Edge of CS to Rising Edge of SCK
Falling Edge of SCK to Rising Edge of CS
SI to SCK Setup Time
SI Hold After SCK Rise
Rise Time of Incoming Signals
Fall Time of Incoming Signals
SO Data Valid to Falling Edge of SCK
Falling Edge of SCK to SO
Rise Time of SO
Fall Time of SO
Falling Edge of CS to SO Operational
(1kPulldown on SO Pin)
fSCK
tSCK
tWH
tWL
tLEAD
tLAG
tSU2
tH2
trSI
tfSI
tSU1
tH1
trSO
tfSO
tSOEN
CL = 200pF
SCK = 0.8V to 0.8V
SCK = 2V TO 2V; fSCK = 1.8MHz
SCK = 0.8V TO 0.8V; fSCK = 1.8MHz
CS = 0.8V to SCK = 2V
SCK = 0.8V to CS = 2V
SI = 0.8, 2V to SCK = 2V;
fSCK = 2.25MHz
SCK = 2V to SI Hold
CL = 200pF
CL = 200pF
SO = 0.8, 2V to SCK = 0.8V; CL = 200pF
SO = 0.8, 2V to SCK = 0.8V; CL = 200pF
CL = 200pF
CL = 200pF
CS = 0.8V to SO Low Impedance
Rising Edge of CS to SO Three-State
(1kPulldown on SO Pin)
tSODIS CS = 2V to SO Three-State
Rising Edge of SCK to SO (Data Valid)
tVALID CL = 200pF, 1.8MHz
CL = 200pF, 2.25MHz
MIN TYP MAX UNITS
1.8 4
- MHz
- 250 555 ns
- 100 248 ns
- 100 248 ns
- 150 200 ns
- 50 200 ns
- 25 55 ns
- 10 55 ns
- - 120 ns
- - 120 ns
80 -
- ns
80 125
-
ns
- 30 50 ns
- 30 50 ns
- 150 300 ns
- 150 200 ns
- - 172 ns
- - 117 ns
CS
SCK
SI
SO
tLEAD
tVALID
tSCK
1
tWL
(MSB = 0)
2
tSU2
tWH
X
tH2
LSB
tLAG
tSODIS
LAST BIT
XMITTED
tSOEN
MSB
tSU1
tH1
LSB
FIGURE 4. TIMING DIAGRAM FOR THE HIP0063 SHOWING THE SPI BUS INPUT CONTROL SIGNALS
5

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