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PDF NLSX5012 Data sheet ( Hoja de datos )
| Número de pieza | NLSX5012 | |
| Descripción | Translator | |
| Fabricantes | ON Semiconductor | |
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NLSX5012
2-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX5012 is a 2-bit configurable dual-supply autosensing
bidirectional level translator that does not require a direction control
pin. The I/O VCC- and I/O VL-ports are designed to track two
different power supply rails, VCC and VL respectively. Both the VCC
and the VL supply rails are configurable from 0.9 V to 4.5 V. This
allows a logic signal on the VL side to be translated to either a higher
or a lower logic signal voltage on the VCC side, and vice-versa.
The NLSX5012 offers the feature that the values of the VCC and
VL supplies are independent. Design flexibility is maximized
because VL can be set to a value either greater than or less than the
VCC supply. In contrast, the majority of competitive auto sense
translators have a restriction that the value of the VL supply must be
equal to less than (VCC - 0.4) V.
The NLSX5012 has high output current capability, which allows
the translator to drive high capacitive loads such as most high
frequency EMI filters. Another feature of the NLSX5012 is that each
I/O_VLn and I/O_VCCn channel can function as either an input or an
output.
An Output Enable (EN) input is available to reduce the power
consumption. The EN pin can be used to disable both I/O ports by
putting them in 3-state which significantly reduces the supply current
from both VCC and VL. The EN signal is referenced to the VL supply.
Features
• Wide VCC, VL Operating Range: 0.9 V to 4.5 V
• VL and VCC are independent
− VL may be greater than, equal to, or less than VCC
• High 100 pF Capacitive Drive Capability
• High−Speed with 140 Mb/s Guaranteed Date Rate
for VCC, VL > 1.8 V
• Low Bit−to−Bit Skew
• Overvoltage Tolerant Enable and I/O Pins
• Non−preferential Power−Up Sequencing
• Power−Off Protection
• Small packaging: UDFN8, SO−8, Micro8
• These are Pb−Free Devices
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
Important Information
• ESD Protection for All Pins:
♦ HBM (Human Body Model) > 8000 V
http://onsemi.com
MARKING
DIAGRAMS
8
1
UDFN8
MU SUFFIX
CASE 517AJ
AE M
G
VA = Specific Device Code
M = Date Code
G = Pb−Free Package
8
1
SO−8
D SUFFIX
CASE 751
8
SX5012
ALYWG
G
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
1
A
Y
W
G
Micro8
DM SUFFIX
CASE 846A
8
5012
AYWG
G
1
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Device
NLSX5012MUTAG
NLSX5012DR2G
Package
Shipping†
UDFN8 3000/Tape & Reel
(Pb−Free)
SO−8 2500/Tape & Reel
(Pb−Free)
NLSX5012DMR2G Micro8 4000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2010
June, 2010 − Rev. 1
1
Publication Order Number:
NLSX5012/D
Free Datasheet http://www.datasheet4u.com/
1 page  
NLSX5012
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
−555C to +1255C
Symbol
Parameter
VIHC I/O VCC Input HIGH Voltage
Test Conditions
(Note 1)
VILC I/O VCC Input LOW Voltage
VIHL I/O VL Input HIGH Voltage
VILL I/O VL Input LOW Voltage
VIH
VIL
VOHC
VOLC
Control Pin Input HIGH
Voltage
Control Pin Input LOW
Voltage
I/O VCC Output HIGH
Voltage
I/O VCC Output LOW Voltage
TA = +25°C
TA = +25°C
I/O VCC source
current = 20 mA
I/O VCC sink
current = 20 mA
VCC (V)
(Note 2)
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
VL (V)
(Note 3)
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
Min
2/3 *
VCC
−
2/3 *
VL
−
2/3 *
VL
−
0.9 *
VCC
−
Typ
(Note 4)
−
−
−
−
−
−
−
−
Max
−
1/3 *
VCC
−
1/3 *
VL
−
1/3 *
VL
−
0.2
Min
2/3 *
VCC
−
2/3 * VL
Max
−
1/3 *
VCC
−
Unit
V
V
V
− 1/3 * VL V
2/3 * VL −
V
− 1/3 * VL V
0.9 * − V
VCC
− 0.2 V
VOHL
VOLL
I/O VL Output HIGH Voltage
I/O VL Output LOW Voltage
I/O VL source
current = 20 mA
I/O VL sink current
= 20 mA
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 *
VL
−
−
−
− 0.9 * VL −
0.2 − 0.2
V
V
IQVCC VCC Supply Current
IQVL VL Supply Current
ITS−VCC VCC Tristate Output Mode
Supply Current
ITS−VL VL Tristate Output Mode
Supply Current
IOZ I/O Tristate Output Mode
Leakage Current
EN = VL, IO = 0 A,
(I/O VCC = 0 V or
VCC, I/O VL = float)
or
(I/O VCC = float, I/O
VL = 0 V or VL)
TA = +25°C,
EN = 0 V
(I/O VCC = 0 V or
VCC, I/O VL = float)
or
(I/O VCC = float, I/O
VL = 0 V or VL)
TA = +25°C,
EN = 0V
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
0.9 – 4.5
−
−
−
−
−
− 1 − 2.5 mA
− 1 − 2.5 mA
− 0.5 − 1.5 mA
− 0.5 − 1.5 mA
− ±1 − ±1.5 mA
II Control Pin Input Current
TA = +25°C
0.9 – 4.5 0.9 – 4.5 −
− ±1 − ±1 mA
IOFF Power Off Leakage Current I/O VCC = 0 to 4.5V,
0
0 − − 1 − 1.5 mA
I/O VL = 0 to 4.5 V 0.9 – 4.5
0
− − 1 − 1.5
0 0.9 – 4.5 − − 1 − 1.5
1. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
2. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
3. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
4. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
http://onsemi.com
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
NLSX5012
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
The NLSX5012 auto−sense translator provides
bi−directional logic voltage level shifting to transfer data
in multiple supply voltage systems. These level translators
have two supply voltages, VL and VCC, which set the logic
levels on the input and output sides of the translator. When
used to transfer data from the I/O VL to the I/O VCC ports,
input signals referenced to the VL supply are translated to
output signals with a logic level matched to VCC. In a
similar manner, the I/O VCC to I/O VL translation shifts
input signals with a logic level compatible to VCC to an
output signal matched to VL.
The NLSX5012 translator consists of bi−directional
channels that independently determine the direction of the
data flow without requiring a directional pin. One−shot
circuits are used to detect the rising or falling input signals.
In addition, the one−shots decrease the rise and fall times
of the output signal for high−to−low and low−to−high
transitions.
Input Driver Requirements
Auto−sense translators such as the NLSX5012 have a
wide bandwidth, but a relatively small DC output current
rating. The high bandwidth of the bi−directional I/O circuit
is used to quickly transform from an input to an output
driver and vice versa. The I/O ports have a modest DC
current output specification so that the output driver can be
over driven when data is sent in the opposite direction. For
proper operation, the input driver to the auto−sense
translator should be capable of driving 2 mA of peak output
current. The bi−directional configuration of the translator
results in both input stages being active for a very short time
period. Although the peak current from the input signal
circuit is relatively large, the average current is small and
consistent with a standard CMOS input stage.
Enable Input (EN)
The NLSX5012 translator has an Enable pin (EN) that
provides tri−state operation at the I/O pins. Driving the
Enable pin to a low logic level minimizes the power
consumption of the device and drives the I/O VCC and I/O
VL pins to a high impedance state. Normal translation
operation occurs when the EN pin is equal to a logic high
signal. The EN pin is referenced to the VL supply and has
Over−Voltage Tolerant (OVT) protection.
Uni−Directional versus Bi−Directional Translation
The NLSX5012 translator can function as a
non−inverting uni−directional translator. One advantage of
using the translator as a uni−directional device is that each
I/O pin can be configured as either an input or output. The
configurable input or output feature is especially useful in
applications such as SPI that use multiple uni−directional
I/O lines to send data to and from a device. The flexible I/O
port of the auto sense translator simplifies the trace
connections on the PCB.
Power Supply Guidelines
The values of the VL and VCC supplies can be set to
anywhere between 0.9 and 4.5 V. Design flexibility is
maximized because VL may be either greater than or less
than the VCC supply. In contrast, the majority of the
competitive auto sense translators has a restriction that the
value of the VL supply must be equal to less than (VCC −
0.4) V.
The sequencing of the power supplies will not damage
the device during power−up operation. In addition, the I/O
VCC and I/O VL pins are in the high impedance state if
either supply voltage is equal to 0 V. For optimal
performance, 0.01 to 0.1 mF decoupling capacitors should
be used on the VL and VCC power supply pins. Ceramic
capacitors are a good design choice to filter and bypass any
noise signals on the voltage lines to the ground plane of the
PCB. The noise immunity will be maximized by placing
the capacitors as close as possible to the supply and ground
pins, along with minimizing the PCB connection traces.
The NLSX5012 translators have a power down feature
that provides design flexibility. The output ports are
disabled when either power supply is off (VL or VCC = 0 V).
This feature causes all of the I/O pins to be in the power
saving high impedance state.
http://onsemi.com
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet NLSX5012.PDF ] | |
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