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PDF NLSX5011 Data sheet ( Hoja de datos )
| Número de pieza | NLSX5011 | |
| Descripción | 1-Bit 100 Mb/s Configurable Dual-Supply Level Translator | |
| Fabricantes | ON Semiconductor | |
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NLSX5011
1-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX5011 is a 1-bit configurable dual-supply autosensing
bidirectional level translator that does not require a direction control
pin. The I/O VCC- and I/O VL-ports are designed to track two
different power supply rails, VCC and VL respectively. Both the VCC
and the VL supply rails are configurable from 0.9 V to 4.5 V. This
allows a logic signal on the VL side to be translated to either a higher
or a lower logic signal voltage on the VCC side, and vice-versa.
The NLSX5011 offers the feature that the values of the VCC and VL
supplies are independent. Design flexibility is maximized because
VL can be set to a value either greater than or less than the VCC
supply. In contrast, the majority of competitive auto sense translators
have a restriction that the value of the VL supply must be equal to less
than (VCC - 0.4) V.
The NLSX5011 has high output current capability, which allows
the translator to drive high capacitive loads such as most high
frequency EMI filters. Another feature of the NLSX5011 is that each
I/O_VLn and I/O_VCCn channel can function as either an input or an
output.
An Output Enable (EN) input is available to reduce the power
consumption. The EN pin can be used to disable both I/O ports by
putting them in 3-state which significantly reduces the supply current
from both VCC and VL. The EN signal is referenced to the VL supply.
Features
• Wide VCC, VL Operating Range: 0.9 V to 4.5 V
• VL and VCC are independent
− VL may be greater than, equal to, or less than VCC
• High 100 pF Capacitive Drive Capability
• High−Speed with 140 Mb/s Guaranteed Date Rate
for VCC, VL > 1.8 V
• Low Bit−to−Bit Skew
• Overvoltage Tolerant Enable and I/O Pins
• Non−preferential Power−Up Sequencing
• Power−Off Protection
• Small packaging: ULLGA6 & UDFN6 Packages
• These are Pb−Free Devices
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
Important Information
• ESD Protection for All Pins:
♦ HBM (Human Body Model) > 8000 V
www.onsemi.com
MARKING
DIAGRAMS
ULLGA6, 1.2x1.0
BMX1 SUFFIX
M
CASE 613AE
1
ULLGA6, 1.45x1.0
AMX1 SUFFIX
M
CASE 613AF
1
UDFN6, 1.2 x 1.0
MU SUFFIX
CASE 517AA
M
1
UDFN6, 1.45 x 1.0
AMU SUFFIX
CASE 517AQ
M
1
E, P, D = Specific Device Code
M = Date Code
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
November, 2015 − Rev. 6
1
Publication Order Number:
NLSX5011/D
1 page  
NLSX5011
TIMING CHARACTERISTICS
−555C to +1255C
Symbol
tR−VCC
Parameter
I/O VCC Rise Time
Test Conditions
(Note 5)
CIOVCC = 15 pF
VCC (V)
(Note 6)
0.9 – 4.5
1.8 – 4.5
VL (V)
(Note 7)
0.9 – 4.5
1.8 – 4.5
Typ
Min (Note 8) Max Unit
− − 8.5 nS
− − 3.5
tF−VCC I/O VCC Fall Time
CIOVCC = 15 pF
0.9 – 4.5
1.8 – 4.5
0.9 – 4.5
1.8 – 4.5
− − 8.5 nS
− − 3.5
tR−VL I/O VL Rise Time
CIOVL = 15 pF
0.9 – 4.5
1.8 – 4.5
0.9 – 4.5
1.8 – 4.5
− − 8.5 nS
− − 3.5
tF−VL I/O VL Fall Time
CIOVL = 15 pF
0.9 – 4.5
1.8 – 4.5
0.9 – 4.5
1.8 – 4.5
− − 8.5 nS
− − 3.5
ZOVCC I/O VCC One−Shot
Output Impedance
(Note 9)
0.9
0.9 – 4.5
− 37 − W
1.8 − 20 −
4.5 − 6.0 −
ZOVL
I/O VL One−Shot Out-
put Impedance
(Note 9)
0.9
0.9 – 4.5
− 37 − W
1.8 − 20 −
4.5 − 6.0 −
tPD_VL−VCC Propagation Delay
(Driving I/O VCC)
CIOVCC = 15 pF
0.9 – 4.5
1.8 – 4.5
0.9 – 4.5
1.8 – 4.5
− − 35 nS
− − 10
CIOVCC = 30 pF
0.9 – 4.5
1.8 – 4.5
0.9 – 4.5
1.8 – 4.5
− − 35
− − 10
CIOVCC = 50 pF
1.0 – 4.5
1.8 – 4.5
1.0 – 4.5
1.8 – 4.5
− − 37
− − 11
CIOVCC = 100 pF
1.2 – 4.5
1.8 – 4.5
1.2 – 4.5
1.8 – 4.5
− − 40
− − 13
tPD_VCC−VL Propagation Delay
(Driving I/O VL)
CIOVL = 15 pF
0.9 – 4.5
1.8 – 4.5
0.9 – 4.5
1.8 – 4.5
− − 35 nS
− − 10
CIOVL = 30 pF
0.9 – 4.5
1.8 – 4.5
0.9 – 4.5
1.8 – 4.5
− − 35
− − 10
CIOVL = 50 pF
1.0 – 4.5
1.8 – 4.5
1.0 – 4.5
1.8 – 4.5
− − 37
− − 11
CIOVL = 100 pF
1.2 – 4.5
1.8 – 4.5
1.2 – 4.5
1.8 – 4.5
− − 40
− − 13
tSK Channel−to−Channel CIOVCC = 15 pF, CIOVL = 15 pF 0.9 – 4.5
Skew
(Note 9)
0.9 – 4.5
− − 0.15 nS
IIN_PEAK
Input Driver Maximum
Peak Current
EN = VL;
I/O_VCC = 1 MHz Square Wave,
Amplitude = VCC, or
I/O_VL = 1 MHz Square Wave,
Amplitude = VL (Note 9)
0.9 – 4.5
0.9 – 4.5
− − 5.0 mA
5. Normal test conditions are VI = 0 V, CIOVCC ≤ 15 pF and CIOVL ≤ 15 pF, unless otherwise specified.
6. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions.
7. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions.
8. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25°C. All units are production tested at TA = +25°C. Limits over the operating
temperature range are guaranteed by design.
9. Guaranteed by design.
www.onsemi.com
5
5 Page 
NLSX5011
PACKAGE DIMENSIONS
UDFN6 1.2 x 1.0, 0.4P
CASE 517AA
ISSUE D
D
PIN ONE
REFERENCE
2X
0.10 C
ÏÏÏÏÏÏ
TOP VIEW
2X
0.10 C
0.10 C
10X 0.08 C
SIDE VIEW
13
A
B
E
(A3)
A
EDGE OF PACKAGE
L1
DETAIL A
Bottom View
(Optional)
EXPOSED Cu
MOLD CMPD
ÏÏÏÏÏÏ A3
A1 DETAIL B
Side View
(Optional)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM MIN MAX
A 0.45 0.55
A1 0.00 0.05
A3 0.127 REF
b 0.15 0.25
D 1.20 BSC
E 1.00 BSC
e 0.40 BSC
L 0.30 0.40
L1 0.00 0.15
L2 0.40 0.50
SEATING
PLANE
A1 C
MOUNTING FOOTPRINT*
6X
0.42
6X
0.22
5X L
L2
6X b
0.10 C A B
0.05 C NOTE 3
6
4
e
BOTTOM VIEW
0.40
PITCH
1.07
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet NLSX5011.PDF ] | |
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