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PDF ADM2491E Data sheet ( Hoja de datos )
| Número de pieza | ADM2491E | |
| Descripción | Half-/Full-Duplex iCoupler Isolated RS-485 Transceiver | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
High Speed, ESD-Protected, Half-/Full-Duplex
iCoupler Isolated RS-485 Transceiver
ADM2491E
FEATURES
Isolated, RS-485/RS-422 transceiver, configurable as half- or
full-duplex
±8 kV ESD protection on RS-485 input/output pins
16 Mbps data rate
Complies with ANSI TIA/EIA RS-485-A-1998 and
ISO 8482: 1987(E)
Suitable for 5 V or 3.3 V operation (VDD1)
High common-mode transient immunity: >25 kV/μs
Receiver has open-circuit, fail-safe design
32 nodes on the bus
Thermal shutdown protection
Safety and regulatory approvals
UL recognition: 5000 V rms isolation voltage
for 1 minute, per UL 1577
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Reinforced insulation, VIORM = 849 V peak
Operating temperature range: −40°C to +85°C
Wide body, 16-lead SOIC package
APPLICATIONS
Isolated RS-485/RS-422 interfaces
Industrial field networks
INTERBUS
Multipoint data transmission systems
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
ADM2491E
DE
Y
TxD
Z
RxD
RE
GND1
Figure 1.
GND2
A
B
GENERAL DESCRIPTION
The ADM2491E is an isolated data transceiver with ±8 kV ESD
protection and is suitable for high speed, half- or full-duplex
communication on multipoint transmission lines. For half-
duplex operation, the transmitter outputs and the receiver
inputs share the same transmission line. Transmitter output
Pin Y is linked externally to receiver input Pin A, and transmit-
ter output Pin Z is linked to receiver input Pin B.
The ADM2491E is designed for balanced transmission lines
and complies with ANSI TIA/EIA RS-485-A-1998 and ISO
8482: 1987(E). The device employs Analog Devices, Inc.,
iCoupler® technology to combine a 3-channel isolator, a three-
state differential line driver, and a differential input receiver into
a single package.
The differential transmitter outputs and receiver inputs feature
electrostatic discharge circuitry that provides protection to
±8 kV using the human body model (HBM). The logic side of
the device can be powered with either a 5 V or a 3.3 V supply,
whereas the bus side requires an isolated 5 V supply.
The device has current-limiting and thermal shutdown features
to protect against output short circuits and situations in which
bus contention could cause excessive power dissipation.
The ADM2491E is available in a wide body, 16-lead SOIC package
and operates over the −40°C to +85°C temperature range.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2007–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADM2491E
TIMING SPECIFICATIONS
TA = −40°C to +85°C.
Table 2.
Parameter
DRIVER
Maximum Data Rate
Propagation Delay
Pulse Width Distortion,
tPWD = |tPYLH − tPYHL|, tPWD = |tPZLH − tPZHL|
Single-Ended Output Rise/Fall Times
Enable Time
Disable Time
RECEIVER
Propagation Delay
Pulse Width Distortion, tPWD = |tPLH − tPHL|
Enable Time
Disable Time
Data Sheet
Symbol Min Typ Max Unit Test Conditions
tPLH, tPHL
tPWD
tR, tF
16
45 60
7
20
55
55
Mbps
ns
ns
ns
ns
ns
RL = 54 Ω, CL1 = C L2 = 100 pF,
see Figure 6 and Figure 10
RL = 54 Ω, CL1 = CL2 = 100 pF,
see Figure 6 and Figure 10
RL = 54 Ω, CL1 = CL2 = 100 pF,
see Figure 6 and Figure 10
RL = 110 Ω, CL = 50 pF, see Figure 8 and
Figure 11
RL = 110 Ω, CL = 50 pF, see Figure 8 and
Figure 11
tPLH, tPHL
tPWD
60 ns
10 ns
13 ns
13 ns
CL = 15 pF, see Figure 7 and Figure 12
CL = 15 pF, see Figure 7 and Figure 12
RL = 1 kΩ, CL = 15 pF, see Figure 9 and
Figure 13
RL = 1 kΩ, CL = 15 pF, see Figure 9 and
Figure 13
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
Input IC Junction-to-Case Thermal Resistance
Output IC Junction-to-Case Thermal Resistance
Symbol
RI-O
CI-O
CI
θJCI
θJCO
Min Typ Max Unit Test Conditions
1012 Ω
3 pF f = 1 MHz
4 pF
33 °C/W Thermocouple located at center
of package underside
28 °C/W
1 Device considered a 2-terminal device: Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together, and Pin 9, Pin 10, Pin 11, Pin 12, Pin 13, Pin 14, Pin 15,
and Pin 16 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
Table 4.
UL1
Recognized under the 1577 component recognition program1
5000 V rms isolation voltage
VDE2
Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-122
Reinforced insulation, 849 V peak
1 In accordance with UL 1577, each ADM2491E is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).
2 In accordance with DIN V VDE V 0884-10, each ADM2491E is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection
limit = 5 pC).
Rev. C | Page 4 of 16
5 Page 
ADM2491E
TYPICAL PERFORMANCE CHARACTERISTICS
2.58
NO LOAD
2.56
2.54
2.52
100Ω LOAD
2.50
2.48 54Ω LOAD
2.46
2.44
2.42
–40
–20
0 20 40
TEMPERATURE (°C)
60
Figure 14. IDD1 Supply Current vs. Temperature
80
60
50
54Ω LOAD
40
100Ω LOAD
30
20
10 NO LOAD
0
–40 –20
0 20 40
TEMPERATURE (°C)
60
Figure 15. IDD2 Supply Current vs. Temperature
80
60
50 tttPPPZYZHLLHHL
40
tPYHL
30
20
10
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
Figure 16. Driver Propagation Delay vs. Temperature
Data Sheet
60
50
40 ttPPLHHL
30
20
10
0
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
Figure 17. Receiver Propagation Delay vs. Temperature
∆: 2.12V
@: 7.72V
TxD
1Z
Y
3 RxD
4
CH1 2V Ω CH2 2V Ω
CH3 2V Ω CH4 2V Ω
M20ns
T 48ns
A CH1 2.32V
Figure 18. Driver/Receiver Propagation Delay, Low to High
(RLDIFF = 54 Ω, CL1 = CL2 = 100 pF)
∆: 2.12V
@: 7.72V
TxD
1
Z
Y
3
RxD
4
CH1 2V Ω CH2 2V Ω
CH3 2V Ω CH4 2V Ω
M20ns
T 48ns
A CH1 3.24V
Figure 19. Driver/Receiver Propagation Delay, High to Low
(RLDIFF = 54 Ω, CL1 = CL2 = 100 pF)
Rev. C | Page 10 of 16
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet ADM2491E.PDF ] | |
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