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PDF HD6413006 Data sheet ( Hoja de datos )

Número de pieza HD6413006
Descripción (HD6413006 / HD6413007) 16-Bit Single-Chip Microcomputer
Fabricantes Renesas 
Logotipo Renesas Logotipo



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To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Free Datasheet http://www.datasheet4u.com/

1 page




HD6413006 pdf
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
The input pins of CMOS products are generally in the high-impedance state. In
operation with an unused pin in the open-circuit state, extra electromagnetic noise is
induced in the vicinity of LSI, an associated shoot-through current flows internally, and
malfunctions may occur due to the false recognition of the pin state as an input signal.
Unused pins should be handled as described under Handling of Unused Pins in the
manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
of the clock signal. Moreover, when switching to a clock signal produced with an
external resonator (or by an external oscillator) while program execution is in progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation
test for each of the products.
Rev.5.00 Sep. 12, 2007 Page iii of xxviii
REJ09B0396-0500
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HD6413006 arduino
Item
Page
8.8.2 Register
Configuration
281
Port B Data Register
(PBDR):
Table 8.16 Port B Pin
Functions
PB3/TP11/TMIO3/DREQ1/
CS4
PB2/TP10/TMO2/CS5
282
PB /TP /TMIO /DREQ /
19
1
0
CS
6
PB /TP /TMO /CS
08
07
283
9.1.4 Register
Configuration
Table 9.3 16-bit timer
Registers
291
Revision (See Manual for Details)
Description amended
The DRAM interface settings by bits DRAS2 to DRAS0 in
DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1 and
CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB,
and bit PB3DDR select the pin function as follows.
Table amended
Pin
PB2/TP10/
TMO2/CS5
Pin Functions and Selection Method
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and
OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR
select the pin function as follows.
DRAM interface
settings
OIS3/2 and
OS1/0
(1) in table below
All 0
Not all 0
(2) in
table
below
CS5E
0 1 ⎯⎯
PB2DDR
NDER10
01
0
1 ⎯ ⎯⎯
1 ⎯ ⎯⎯
Pin function
PB2
input
PB2
output
TP10
output
CS5
output
TMO2
output
CS5
output*
Description amended
Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in
8TCR0, bit CS6E in CSCR, bit NDER9 in NDERB, and bit
PB1DDR select the pin function as follows.
Description amended
Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit
NDER8 in NDERB, and bit PB0DDR select the pin function as
follows.
Table amended
Channel
Common
Address*1
H'FFF64
Name
Timer interrupt status register A
Abbre-
viation
TISRA
R/W
Initial
Value
R/(W)*2 H'88
Rev.5.00 Sep. 12, 2007 Page ix of xxviii
REJ09B0396-0500
Free Datasheet http://www.datasheet4u.com/

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