|
|
PDF FDMF6705V Data sheet ( Hoja de datos )
| Número de pieza | FDMF6705V | |
| Descripción | High-Frequency DrMOS Module | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de FDMF6705V (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
March 2011
FDMF6705V – XS™ DrMOS – Extra-Small, High-
Performance, High-Frequency DrMOS Module
Benefits
Single 12V Input Power Supply Operation
Ultra-Compact 6x6mm PQFN, 72% Space-Saving
Compared to Conventional Discrete Solutions
Fully Optimized System Efficiency
Clean Switching Waveforms with Minimal Ringing
High-Current Handling
Description
The XS™ DrMOS family is Fairchild’s next-generation,
fully optimized, ultra-compact, integrated MOSFET plus
driver power stage solutions for high-current, high-
frequency, synchronous buck DC-DC applications. The
FDMF6705V integrates a driver IC, two power
MOSFETs, and a bootstrap Schottky diode into a
thermally enhanced, ultra-compact 6x6mm PQFN
package.
Features
Over 93% Peak-Efficiency
High-Current Handling of 43A
High-Performance PQFN Copper Clip Package
3-State 5V PWM Input Driver
Shorter Propagation Delays than FDMF6704V
Shorter Dead Times than FDMF6704V
Skip-Mode SMOD# (Low-Side Gate Turn Off) Input
Thermal Warning Flag for Over-Temperature
Condition
Driver Output Disable Function (DISB# Pin)
Internal Pull-Up and Pull-Down for SMOD# and
DISB# Inputs, Respectively
Fairchild PowerTrench® Technology MOSFETs for
Clean Voltage Waveforms and Reduced Ringing
Fairchild SyncFET™ (Integrated Schottky Diode)
Technology in the Low-Side MOSFET
Integrated Bootstrap Schottky Diode
Adaptive Gate Drive Timing for Shoot-through
Protection
Under-Voltage Lockout (UVLO)
Optimized for Switching Frequencies up to 1MHz
Low-Profile SMD Package
Fairchild Green Packaging and RoHS Compliant
Based on the Intel® 4.0 DrMOS Standard
With an integrated approach, the complete switching
power stage is optimized with regards to driver and
MOSFET dynamic performance, system inductance,
and Power MOSFET RDS(ON). XS™ DrMOS uses
Fairchild's high-performance PowerTrench® MOSFET
technology, which dramatically reduces switch ringing,
eliminating the need for a snubber circuit in most buck
converter applications.
A new driver IC with reduced dead times and
propagation delays further enhances the performance
of this part. A thermal warning function has been
included to warn of a potential over-temperature
situation. The FDMF6705V also incorporates features,
such as Skip Mode (SMOD), for improved light-load
efficiency along with a 3-state PWM input for
compatibility with a wide range of PWM controllers.
Applications
High-Performance Gaming Motherboards
Compact Blade Servers, V-Core and Non-V-Core
DC-DC Converters
Desktop Computers, V-Core and Non-V-Core
DC-DC Converters
Workstations
High-Current DC-DC Point-of-Load (POL)
Converters
Networking and Telecom Microprocessor Voltage
Regulators
Small Form-Factor Voltage Regulator Modules
Ordering Information
Part
Number
Current
Rating
Input
Voltage
FDMF6705V
40A
12V
Switching
Frequency
Package
1000kHz
40-Lead, Clipbond PQFN DrMOS,
6.0x6.0mm Package
© 2011 Fairchild Semiconductor Corporation
FDMF6705V • Rev. 1.0 1
Top Mark
FDMF6705V
www.fairchildsemi.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Electrical Characteristics
Typical values are VIN=12V, VDRV=12V, and TA=+25°C unless otherwise noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
IDRV Operating Current
Internal 5V Linear Regulator
VDRV=14V, PWM=LOW or HIGH or Float
2 5 mA
VDRV
IDRV
VCIN
PVDRV
CVCIN
VRLINE
VRLOAD
Input Voltage
Input Current
Output Voltage
Power Dissipation
VCIN Bypass Capacitor
Line Regulation
Load Regulation
Short-Circuit Current Limit
8V<VIN<14V, fSW=1MHz
VDRV=8V, ILOAD=5mA
VDRV=12V, fSW=1MHz
X7R or X5R Ceramic
8V<VIN<14V, ILOAD=5mA
VDRV=8V, 5mA<ILOAD<100mA
8 12 14 V
36 mA
4.8 5.0 5.2 V
250 mW
1 10 µF
20 mV
75 mV
200 mA
UVLO UVLO Threshold
UVLO_Hyst UVLO Hysteresis
PWM Input
VDRV Rising
6.8 7.3 7.8
0.435
V
V
RUP_PWM Pull-Up Impedance
RDown_PWM Pull-Down Impedance
VIH_PWM PWM High Level Voltage
VTRI_HI 3-State Rising Threshold
VTRI_LO 3-State Falling Threshold
VIL_PWM PWM Low Level Voltage
tD_HOLD-OFF 3-State Shutoff Time
VHiZ_PWM 3-State Open Voltage
DISB# Input
3.30
3.20
1.00
0.85
2.3
10
10
3.55
3.45
1.25
1.15
160
2.5
3.80
3.70
1.50
1.40
200
2.7
kΩ
kΩ
V
V
V
V
ns
V
VIH_DISB
VIL_DISB
IPLD
tPD_DISBL
High-Level Input Voltage
Low-Level Input Voltage
Pull-Down Current
Propagation Delay
PWM=GND, Delay Between DISB# from
HIGH to LOW to GL from HIGH to LOW
2V
0.8 V
10 µA
25 ns
tPD_DISBH Propagation Delay
PWM=GND, Delay Between DISB# from
LOW to HIGH to GL from LOW to HIGH
25 ns
SMOD# Input
VIH_SMOD
VIL_SMOD
IPLM
High-Level Input Voltage
Low-Level Input Voltage
Pull-Up Current
tPD_SLGLL Propagation Delay
PWM=GND, Delay Between SMOD# from
HIGH to LOW to GL from HIGH to LOW
2V
0.8 V
10 µA
10 ns
tPD_SHGLH Propagation Delay
PWM=GND, Delay Between SMOD# from
LOW to HIGH to GL from LOW to HIGH
10 ns
Continued on the following page…
© 2011 Fairchild Semiconductor Corporation
FDMF6705V • Rev. 1.0.1
5
www.fairchildsemi.com
Free Datasheet http://www.datasheet4u.com/
5 Page 
Functional Description
The FDMF6705V is a driver-plus-FET module optimized
for the synchronous buck converter topology. A single
PWM input signal is all that is required to properly drive
the high-side and the low-side MOSFETs. Each part is
capable of driving speeds up to 1MHz.
VDRV and Disable
The VDRV pin is monitored by an under-voltage lockout
(UVLO) circuit. When VDRV rises above ~7.3V, the driver
is enabled for operation. When VDRV falls below ~6.95V,
the driver is disabled (GH, GL=0). The driver can also
be disabled by pulling the DISB# pin LOW (DISB# <
VIL_DISB), which holds both GL and GH LOW regardless
of the PWM input state. The driver can be enabled by
raising the DISB# pin voltage HIGH (DISB# > VIH_DISB).
Table 1. UVLO and Disable Logic
UVLO
0
1
1
1
DISB#
X
0
1
Open
Driver State
Disabled (GH, GL=0)
Disabled (GH, GL=0)
Enabled (See Table 2)
Disabled (GH, GL=0)
Note:
3. DISB# has an internal pull-down current source of
10µA.
Thermal Warning Flag
The FDMF6705V provides a thermal warning flag
(THWN) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN output returns to a high-
impedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN output
requires a pull-up resistor, which can be connected to
VCIN. THWN does NOT disable the DrMOS module.
135°C 150°C
Reset Activation
High Temp. Temp.
Normal
Operation
Low
TJ_driver IC
Thermal
Warning
Figure 23. THWN Operation
3-State PWM Input
The FDMF6705V incorporates a 3-state PWM input
gate drive design. The 3-state gate drive has both logic
HIGH level and LOW level, along with a 3-state
shutdown window. When the PWM input signal enters
and remains within the 3-state window for a defined
hold-off time (tD_HOLD-OFF), both GL and GH are pulled
LOW. This feature enables the gate drive to shut down
both high-and low-side MOSFETs to support features
such as phase shedding, which is a common feature on
multiphase voltage regulators.
Operation when Exiting 3-State Condition
When exiting a valid 3-state condition, the FDMF6705V
design follows the PWM input command. If the PWM
input goes from 3-state to LOW, the low side MOSFET
is turned on. If the PWM input goes from 3-state to
HIGH, the high-side MOSFET is turned on. This is
illustrated in Figure 24. The FDMF6705V design allows
for short propagation delays when exiting the 3-state
window (see Electrical Characteristics).
Low-Side Driver
The low-side driver (GL) is designed to drive a ground-
referenced low RDS(ON) N-channel MOSFET. The bias
for GL is internally connected between VCIN and
CGND. When the driver is enabled, the driver's output
is 180° out of phase with the PWM input. When the
driver is disabled (DISB#=0V), GL is held LOW.
High-Side Driver
The high-side driver is designed to drive a floating N-
channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit,
consisting of the internal Schottky diode and external
bootstrap capacitor (CBOOT). During startup, VSWH is
held at PGND, allowing CBOOT to charge to VCIN
through the internal diode. When the PWM input goes
HIGH, GH begins to charge the gate of the high-side
MOSFET (Q1). During this transition, the charge is
removed from CBOOT and delivered to the gate of Q1. As
Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to
VIN + VBOOT, which provides sufficient VGS enhancement
for Q1. To complete the switching cycle, Q1 is turned off
by pulling GH to VSWH. CBOOT is then recharged to
VCIN when VSWH falls to PGND. GH output is in-
phase with the PWM input. The high-side gate is held
LOW when the driver is disabled or the PWM signal is
held within the 3-state window for longer than the 3-
state hold-off time, tD_HOLD-OFF.
© 2011 Fairchild Semiconductor Corporation
FDMF6705V • Rev. 1.0.1
11
www.fairchildsemi.com
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet FDMF6705V.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| FDMF6705 | High-Frequency DrMOS Module | Fairchild Semiconductor |
| FDMF6705B | High-Frequency DrMOS Module | Fairchild Semiconductor |
| FDMF6705V | High-Frequency DrMOS Module | Fairchild Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |