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PDF TC58NVG6D2GTA00 Data sheet ( Hoja de datos )
| Número de pieza | TC58NVG6D2GTA00 | |
| Descripción | 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA CONFIDENTIAL TC58NVG6D2GTA00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64 GBIT (8G 8 BIT) CMOS NAND E2PROM (Multi-Level-Cell)
DESCRIPTION
The TC58NVG6D2 is a single 3.3 V 64 Gbit (74,594,648,064 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (8192 + 640) bytes 256 pages 4124 blocks.
The device has two 8832-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 8832-byte increments. The Erase operation is implemented in a single block
unit (2 Mbytes 160 Kbytes: 8832 bytes 256 pages).
The TC58NVG6D2 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Memory cell array
Register
Page size
Block size
TC58NVG6D2G
8832 512K 8
8832 8
8832 bytes
(2M 160 K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 3996 blocks
Max 4124 blocks
Power supply
VCC 2.7 V to 3.6 V
Access time
Cell array to register 200 s max
Serial Read Cycle
25 ns min
Program/Erase time
Auto Page Program
Auto Block Erase
1400 s/page typ.
5 ms/block typ.
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
TBD ( 30 mA max.)
TBD ( 30 mA max.)
TBD ( 30 mA max.)
50 A max
Package
(Weight: TBD g typ.)
FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (17).
1 2010-08-02C
Free Datasheet http://www.datasheet4u.com/
1 page  
TOSHIBA CONFIDENTIAL TC58NVG6D2GTA00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta 0 to 70℃, VCC 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tCLS
CLE Setup Time
10 ns
tCLS2
CLE Setup Time
40 ns
tCLH
CLE Hold Time
5 ns
tCS CE Setup Time
20 ns
tCS2
CE Setup Time
32 ns
tCH CE Hold Time
5 ns
tWP Write Pulse Width
12 ns
tALS
ALE Setup Time
10 ns
tALH
ALE Hold Time
5 ns
tDS Data Setup Time
10 ns
tDH Data Hold Time
5 ns
tWC Write Cycle Time
25 ns
tWH WE High Hold Time
10 ns
tWHW *
WE High Hold Time from final address to first data
300 ns
tWW
WP High to WE Low
100 ns
tRR Ready to RE Falling Edge
20 ns
tRW Ready to WE Falling Edge
20 ns
tRP Read Pulse Width
12 ns
tRC Read Cycle Time
25 ns
tREA
RE Access Time
20 ns
tCR CE Low to RE Low
10 ns
tCLR
CLE Low to RE Low
10 ns
tAR ALE Low to RE Low
10 ns
tRHOH
Data Output Hold Time from RE High
25 ns
tRLOH
Data Output Hold Time from RE Low
5 ns
tRHZ
RE High to Output High Impedance
60 ns
tCHZ
CE High to Output High Impedance
30 ns
tCLHZ
CLE High to Output High Impedance
30 ns
tREH
RE High Hold Time
10 ns
tIR Output-High-impedance-to- RE Falling Edge
0 ns
tRHW
RE High to WE Low
30 ns
tWHC
WE High to CE Low
30 ns
tWHR1
WE High to RE Low (Status Read)
180 ns
tWHR2
WE High to RE Low (Column Address Change in Read)
300 ns
tR Memory Cell Array to Starting Address
200 s
tDCBSYR1 Data Cache Busy in Read Cache (following 31h and 3Fh)
200 s
tDCBSYR2 Data Cache Busy in Page Copy (following 3Ah)
205 s
tWB WE High to Busy
100 ns
tRST
Device Reset Time (Ready/Read/Program/Erase)
10/10/30/100
s
* tWHW is the time from the WE rising edge of final address cycle to the WE falling edge of first data cycle.
5 2010-08-02C
Free Datasheet http://www.datasheet4u.com/
5 Page 
TOSHIBA CONFIDENTIAL TC58NVG6D2GTA00
ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
CLE
CE
WE
ALE
RE
I/O
tCR
tWHR1
tAR
tREA
90h 00h
98h DEh
ID Read Address 00
command
Maker code Device code
See
table 5
See
table 5
See
table 5
Table 5. Code table
Description
1st Data
2nd Data
3rd Data
4th Data
5th Data
Maker Code
Device Code
Chip Number, Cell Type
Page Size, Block Size
Plane Number
3rd Data
Internal Chip Number
Cell Type
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
10011000
11011110
Hex Data
98h
DEh
See table
See table
See table
Description
1
2
4
8
2 level cell
4 level cell
8 level cell
16 level cell
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
00
01
10
11
00
01
10
11
50
2010-08-02C
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet TC58NVG6D2GTA00.PDF ] | |
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