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TC58NVG6DDJTA00 fiches techniques PDF

Toshiba - 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM

Numéro de référence TC58NVG6DDJTA00
Description 64 GBIT (8G X 8 BIT) CMOS NAND E2PROM
Fabricant Toshiba 
Logo Toshiba 





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TC58NVG6DDJTA00 fiche technique
TOSHIBA CONFIDENTIAL TC58NVG6DDJTA00
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
64 GBIT (8G × 8 BIT) CMOS NAND E2PROM (Multi-Level-Cell)
DESCRIPTION
The TC58NVG6DD is a single 3.3 V 64 Gbit (77,054,607,360 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E2PROM) organized as (16384 + 1280) bytes × 256 pages × 2130 blocks.
The device has two 17664-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 17664-byte increments. The Erase operation is implemented in a single block
unit (4 Mbytes + 320 Kbytes: 17664 bytes × 256 pages).
The TC58NVG6DD is a serial-type memory device which utilizes the DQ pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
Organization
Device capacity
Register
Page size
Block size
TC58NVG6DDJTA00
17664 × 256 × 2130 × 8 bits
17664 × 8 bits
17664 bytes
(4M + 320 K) bytes
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 2018 blocks
Max 2130 blocks
Power supply
VCC = 2.7 V to 3.6 V
Access time
Cell array to register 50 μs typ. (TBD)
100 μs max (TBD)
Serial Read Cycle
20 ns min
Program/Erase time
Auto Page Program
Auto Block Erase
1400 μs/page typ.(TBD)
5 ms/block typ.(TBD)
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
TBD mA max (per 1 chip)
TBD mA max (per 1 chip)
TBD mA max (per 1 chip)
TBD μA max (per 1 chip)
Package
(Weight: TBD g typ.)
FOR RELIABILITY GUIDANCE, PLEASE REFER TO THE APPLICATION NOTES AND COMMENTS (17).
1 2011-07-27C
Free Datasheet http://www.datasheet4u.com/

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