TC58NVG0S3ETA00 Datasheet PDF - Toshiba
| Part Number | TC58NVG0S3ETA00 | |
| Description | 1 GBIT (128M X 8 BIT) CMOS NAND E2PROM | |
| Manufacturers | Toshiba | |
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TC58NVG0S3ETA00
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1 GBIT (128M × 8 BIT) CMOS NAND E2PROM
DESCRIPTION
The TC58NVG0S3E is a single 3.3V 1 Gbit (1,107,296,256 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as (2048 + 64) bytes × 64 pages × 1024blocks.
The device has two 2112-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 4 Kbytes: 2112 bytes × 64 pages).
The TC58NVG0S3E is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
• Organization
Memory cell array
Register
Page size
Block size
x8
2112 × 64K × 8
2112 × 8
2112 bytes
(128K + 4K) bytes
• Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
• Mode control
Serial input/output
Command control
• Number of valid blocks
Min 1004 blocks
Max 1024 blocks
• Power supply
VCC = 2.7V to 3.6V
• Access time
Cell array to register 25 µs max
Serial Read Cycle
25 ns min (CL=100pF)
• Program/Erase time
Auto Page Program
Auto Block Erase
300 µs/page typ.
2.5 ms/block typ.
• Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
30 mA max.
30 mA max
30 mA max
50 µA max
• Package
TSOP I 48-P-1220-0.50 (Weight: 0.53 g typ.)
1 2011-03-01C
Free Datasheet http://www.datasheet4u.com/
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TC58NVG0S3ETA00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70 , VCC = 2.7 to 3.6V)
SYMBOL
PARAMETER
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tWW
tRR
tRW
tRP
tRC
tREA
tCEA
tCLR
tAR
tRHOH
tRLOH
tRHZ
tCHZ
tCSD
tREH
tIR
tRHW
tWHC
tWHR
tR
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time
CE Access Time
CLE Low to RE Low
ALE Low to RE Low
RE High to Output Hold Time
RE Low to Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
CE High to ALE or CLE Don’t Care
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE High to WE Low
WE High to CE Low
WE High to RE Low
Memory Cell Array to Starting Address
tDCBSYR1
Data Cache Busy in Read Cache (following 31h and
3Fh)
MIN
12
5
20
5
12
12
5
12
5
25
10
100
20
20
12
25
⎯
⎯
10
10
22
5
⎯
⎯
0
10
0
30
30
60
⎯
⎯
MAX
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
20
25
⎯
⎯
⎯
⎯
60
20
⎯
⎯
⎯
⎯
⎯
⎯
25
30
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
tDCBSYR2
Data Cache Busy in Page Copy (following 3Ah)
tWB WE High to Busy
tRST
Device Reset Time (Ready/Read/Program/Erase)
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
5
⎯ 35 µs
⎯ 100 ns
⎯
6/6/10/500
µs
2011-03-01C
Free Datasheet http://www.datasheet4u.com/
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for TC58NVG0S3ETA00 electronic component. |
| Information | Total 65 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ TC58NVG0S3ETA00.PDF Datasheet ] | |
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