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PDF R8A66155SP Data sheet ( Hoja de datos )

Número de pieza R8A66155SP
Descripción 16-bit I/O EXPANDER
Fabricantes Renesas 
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R8A66155SP
16-bit I/O EXPANDER WITH LED DRIVE FUNCTION
REJ03F0286-0100
Rev. 1.00
Dec.08.2009
DESCRIPTION
R8A66155 is a semiconductor integrated circuit which has 16-bit shift register function to execute serial in -
parallel out conversion and parallel in - serial out conversion.
Built in two shift registers for serial in - parallel out and parallel in - serial out are constructed independently,
This IC is able to read serial input data into a shift register while output the serial data converting from the
parallel data input.
Also, parallel data I/O pins can be set to input mode or output mode by a bit.
R8A66155 is useful in a wide range of applications, such as MCU (micro controller unit) I/O port extension
and serial bus system data communication.
Moreover, R8A66155 can be used as the anode common LED drive, too.
FEATURES
Bi-directional serial communication with MCU
Serial data can be input during parallel to serial data conversion
Parallel data I/O pins can be set input mode or output mode by a bit
Schmitt input (DI, CLK, /S, /CS)
N-ch open drain output (DO, D1~D16).
High output current IOL=24mA (at VCC=4.5V), IOL=15mA (at VCC=3.0V)
Parallel data I/O pins (D1~D16)
Wide supply voltage range (Vcc=2.0 to 6.0V)
Wide operating temperature range (Ta=-40 to 85)
APPLICATION
Serial - parallel or parallel - serial data conversion for MCU peripheral.
Serial bus control by MCU.
LED array drive, The various LED display modules.
PIN CONFIGURATION (TOP VIEW)
SERIAL DATA OUTPUT DO
SERIAL DATA INPUT DI
CLOCK INPUT CLK
CHIP SELECT INPUT CS
Vcc
SET INPUT S
GND
D16
PARALLEL DATA I/O
D15
D14
D13
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 D1
23 D2
22 D3
21 D4
20 D5
19 D6
PARALLEL DATA I/O
18 D7
17 D8
16 D9
15 D10
14 D11
13 D12
REJ03F0286-0100 Rev.1.00 Dec.08.2009
Page 1 of 7
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R8A66155SP pdf
R8A66155SP
SWITCHING CHARACTERISTICS
Symbol
Parameter
fmax
tPLZ
tPZL
tPLZ
tPZL
tPLZ
Maximum repeat frequency
Output "L-Z" and "Z-L" propagation time
CLK - DO
Output "L-Z" and "Z-L" propagation time
/CS - D1~D16
Output "L-Z" propagation time
/S - DO, /S - D1~D16
(Vcc=2.0~6.0V, Ta=-40~85, unless otherwise noted)
Test conditions Min.
CL=50pF
RL=1kΩ
(note1)
Limits
Typ.
Max.
1.9
400
400
400
400
400
Unit
MHz
ns
ns
ns
ns
ns
TIMING REQUIREMENTS (Vcc=2.0~6.0V, Ta=-40~85, unless otherwise noted)
Symbol
Parameter
tw CLK, /CS, /S pulse width
Setup time of DI to CLK
tsu Setup time of /CS to CLK
Setup time of D1~D16 to /CS
Hold time of DI to CLK
th Hold time of /CS to CLK
Hold time of D1~D16 to /CS
trec Recovery time of /CS to /S
Test conditions
Min.
260
130
130
130
130
130
130
130
Limits
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NOTE1: TEST CIRCUIT
Input
Vcc
P.G.
50Ω
DUT
GND
(1) The pulse generator (P.G.) has the following characteristics
(10%~90%) tr=6ns, tf=6ns, Zo=50 Ω
(2) The capacitance CL includes stray wiring capacitance
and the probe input capacitance.
Vcc
RL
CL
DO,
D1D16
REJ03F0286-0100 Rev.1.00 Dec.08.2009
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