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PDF 20T202DA1J Data sheet ( Hoja de datos )
| Número de pieza | 20T202DA1J | |
| Descripción | VFD Module | |
| Fabricantes | Samsung | |
| Logotipo |  |
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DISPLAY DEVICES
20T202DA1J (Tentative)
Page - 1 / 18
VACUUM FLUORESCENT DISPLAY MODULE
Free Datasheet http://www.datasheet4u.com/
1 page  
DISPLAY DEVICES
20T202DA1J (Tentative)
4.8.4 M68 type CPU bus write-in Timing
R/W
tSU(RS,R/W)
Min 20ns
tH(RS.R/W)
Min 10ns
Page - 5 / 18
RS
E
DB0¡-DB7
tWL(E)
Min 230ns
tWH(E)
Min 230ns
tCYC(E)
Min 500ns
tSU(data)
Min 80ns
tHWR(data)
Min 10ns
VALID
Fig-4 Data write-in Timing Diagram (M68 bus interface)
4.8.5 M68 type CPU bus read-out Timing
R/W
tSU(RS,R/W)
Min 20ns
tH(RS.R/W)
Min 10ns
RS
E
DB0¡-DB7
tWL(E)
Min 230ns
tWH(E)
Min 230ns
tCYC(E)
Min 500ns
tDELAY(data)
Max 160ns
tHRD(data)
Min 5ns
VALID
Fig-5 Data read-out Timing Diagram (M68 bus interface)
4.9 Connector Pin Assignment
Fourteen of through holes are prepared for power supply
and signal interface. A connector may be able to soldered
to the holes. Location and dimensions are showen at Fig-8
on page 7/18.
¡Ø The third hole (pin #3) can be used for reset input if the
soldering pad "JP1" is short-circuited.
(Refer to "Fig-6 System Block Diagram" on next page.)
No. Signal
No. Signal
1 GND
8 DB1
2 Vcc
9 DB2
3 ¡Ø /RST
10
DB3
4 RS
11 DB4
5 R/W(/WR)
12
DB5
6 E(/RD) 13 DB6
7 DB0
14 DB7
Free Datasheet http://www.datasheet4u.com/
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DISPLAY DEVICES
20T202DA1J (Tentative)
Page - 11 / 18
5.2 Interfacing to the MPU
This VFD module can interface in either two 4-bit operations or one 8-bit operation, thus allowing
interfacing with 4- or 8-bit MPUs.
* For 4-bit interface data, only four bus lines (DB4 to DB7) are used for transfer. When to use 4-bit
parallel data transfer, DB0 to DB3 keep "H" or "L". The data transfer between the VFD module and
the MPU is completed after the 4-bit data has been transferred twice. As for the order of data transfer
the four high order bits (for 8-bit operation, DB4 to DB7) are transferred before the four low order bits
(for 8-bit operation, DB0 to DB3).
The busy flag (BF) are performed before transferring the higher 4 bits. BF checks are not required
before transferring the lower 4 bits.
RS
R/W
E
DB7
DB6
DB5
DB4
IR7 IR3
D7 D3
BF AC3 DR7 DR3
IR6 IR2
D6 D2
AC6 AC2 DR6 DR2
IR5 IR1
D5 D1
AC5
AC1
DR5 DR1
IR4 IR0
Instruction Register
Write
D4 D0
Character Code
Write
AC4 AC0
Busy Flag & Address
Counter Read
DR4 DR0
Data Register
Read
Fig-11 4-Bit Transfer Example (M68)
* For 8-bit interface data, all eight bus lines (DB0 to DB7) are used.
D7 D3
D6 D2
D5 D1
D4 D0
Character Code
Write
5.3 Reset Function
5.3.1 Power-on reset
An internal reset circuit automatically initializes the module when the power is turned on.
The following instructions are executed during the initialization.
1) Display clear
Fill the DD-RAM with 20H (Space Code)
2) Set the addres counter to 00H
Set the address counter (ACC) to point DD-RAM.
3) Display on/off control:
D=0
; Display off
C=0
; Cursor off
B=0
; Blinking off
4) Entry mode set:
I/D = 1
; Increment by 1
S=0
; No shift
5) Function Set
IF = 1
; 8-bit interface data
N=1
; 2-line display
BR0 = BR1 =0 ; Brightness = 100%
6) CPU interface type
when JP0 = Open ; M68 type (Factory Setting)
when JP0 = Short ; i80 type
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet 20T202DA1J.PDF ] | |
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