PDF AD9139 Data sheet ( Hoja de datos )

Número de pieza	AD9139
Descripción	Digital-to-Analog Converter
Fabricantes	Analog Devices
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Data Sheet 16-Bit, 1600 MSPS, TxDAC+ Digital-to- Analog Converter AD9139 FEATURES GENERAL DESCRIPTION Selectable 1× or 2× interpolation filter Support input signal bandwidth up to 575 MHz Very small inherent latency variation: <2 DAC clock cycles Proprietary low spurious and distortion design 6-carrier GSM ACLR = 79 dBc at 200 MHz IF SFDR >85 dBc (bandwidth = 300 MHz) at zero IF Flexible 16-bit LVDS interface Supports word and byte load Multiple chip synchronization Fixed latency and data generator latency compensation FIFO eases system timing and includes error detection High performance, low noise PLL clock multiplier Digital inverse sinc filter Low power: 700 mW at 1230 MSPS 72-lead LFCSP APPLICATIONS Wireless communications: 3G/4G and MC-GSM base stations, wideband repeaters, software defined radios Wideband communications: point-to-point, LMDS/MMDS Transmit diversity/MIMO Instrumentation Automated test equipment The AD9139 is an 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9139 TxDAC+® includes features optimized for wideband communication applications, including 1× and 2× interpolation, a delay locked loop (DLL) powered high speed interface, sample error detection, and parity detection. A 3-wire serial port interface provides for the programming/readback of many internal parameters. A full-scale output current can be programmed over a range of 9 mA up to 33 mA. The AD9139 is available in a 72-lead LFCSP. PRODUCT HIGHLIGHTS 1. 575 MHz achievable input signal bandwidth. 2. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. 3. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. 4. Low power architecture improves power efficiency. FUNCTIONAL BLOCK DIAGRAM DCIP/DCIN D15P/D15N D0P/D0N FRAMEP/PARITYP FRAMEN/PARITYN DLL 13-TAP AD9139 HB1 2× 16 DAC 1 16-BIT DAC_CLK DACOUTP DACOUTN INTERNAL CLOCK TIMING AND CONTROL LOGIC REF 10 AND BIAS VREF FSADJ PROGRAMMING REGISTERS SERIAL INPUT/OUTPUT PORT POWER-ON MULTICHIP RESET SYNCHRONIZATION DAC_CLK SYNC CLOCK MULTIPLIER CLK RCVR REF RCVR DACCLKP DACCLKN REFP/SYNCP REFN/SYNCN Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com Free Datasheet http://www.datasheet4u.com/ 1 page Data Sheet AD9139 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input Logic High Logic Low CMOS OUTPUT LOGIC LEVEL Output Logic High Logic Low LVDS RECEIVER INPUTS Input Voltage Range Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance DLL SPEED RANGE DAC UPDATE RATE DAC Adjusted Update Rate DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage REFCLK/SYNCCLK INPUT (REFP/SYNCP, REFN/SYNCN) Differential Peak-to-Peak Voltage Common-Mode Voltage Input Clock Frequency SERIAL PORT INTERFACE Maximum Clock Rate Minimum Pulse Width High Low SDIO to SCLK Setup Time SDIO to SCLK Hold Time CS to SCLK Setup Time CS to SCLK Hold Time SDIO to SCLK Delay SDIO High-Z to CS SDIO LOGIC LEVEL Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Symbol Test Conditions/Comments Min Typ Max Unit DVDD18 = 1.8 V DVDD18 = 1.8 V 1.2 V 0.6 V VIA or VIB VIDTH VIDTHH to VIDTHL RIN DVDD18 = 1.8 V DVDD18 = 1.8 V Data and frame inputs 1× interpolation 2× interpolation Self biased input, ac-coupled 1.4 0.4 825 1675 −175 +175 20 100 250 575 1600 1150 800 100 500 2000 1.25 V V mV mV mV Ω MHz MSPS MSPS MSPS mV V SCLK tPWH tPWL tDS tDH tDCSB tDCSB tDV VIH VIL IIH IIL 1.03 GHz ≤ fVCO ≤ 2.07 GHz 100 500 2000 1.25 450 40 12.5 12.5 1.5 0.68 2.38 1.4 9.6 Wait time for valid output from 11 SDIO Time for SDIO to relinquish the 8.5 output bus With 2 mA loading With 2 mA loading 1.2 1.8 0 0.5 1.36 2 0 0.45 mV V MHz MHz ns ns ns ns ns ns ns ns V V V V Rev. 0 \| Page 5 of 56 Free Datasheet http://www.datasheet4u.com/ 5 Page Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS –40 fDAC = 737.28MHz fDAC = 983.04MHz –50 fDAC = 1228.8MHz –60 –70 –80 –90 –100 0 100 200 300 400 500 600 700 fOUT (MHz) Figure 3. Single-Tone (0 dBFS) SFDR vs. fOUT in the First Nyquist Zone over fDAC –40 0dBFS –6dBFS –50 –12dBFS –16dBFS –60 –70 –80 –90 –100 0 100 200 300 400 500 600 700 fOUT (MHz) Figure 4. Single-Tone Second Harmonic vs. fOUT in the First Nyquist Zone over Digital Back Off, fDAC = 1228.8 MHz –40 0dBFS –6dBFS –50 –12dBFS –16dBFS –60 –70 –80 –90 –100 0 100 200 300 400 500 600 700 fOUT (MHz) Figure 5. Single-Tone Third Harmonic vs. fOUT in the First Nyquist Zone over Digital Back Off, fDAC = 1228.8 MHz AD9139 –40 fDAC = 800MHz –50 fDAC = 1600MHz 0dBFS –12dBFS –60 –70 –80 –90 –100 0 50 100 150 200 250 300 350 400 fOUT (MHz) Figure 6. Single-Tone SFDR Excluding 2nd and 3rd Harmonics vs. fOUT in the First Nyquist Zone over fDAC and Digital Back Off –40 fDAC = 737.28MHz fDAC = 983.04MHz –50 fDAC = 1228.8MHz –60 –70 –80 –90 –100 0 100 200 300 400 500 600 fOUT (MHz) Figure 7. Two-Tone Third IMD vs. fOUT over fDAC 700 –40 0dBFS –6dBFS –50 –12dBFS –16dBFS –60 –70 –80 –90 –100 0 100 200 300 400 500 600 700 fOUT (MHz) Figure 8. Two-Tone Third IMD vs. fOUT over Digital Back Off, fDAC = 1228.8 MHz Rev. 0 \| Page 11 of 56 Free Datasheet http://www.datasheet4u.com/ 11 Page

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