PDF NCN5192 Data sheet ( Hoja de datos )

Número de pieza	NCN5192
Descripción	HART Modem
Fabricantes	ON Semiconductor
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No Preview Available ! NCN5192 HART Modem Description The NCN5192 is a single−chip, CMOS modem for use in highway addressable remote transducer (HART) field instruments and masters. The modem and a few external passive components provide all of the functions needed to satisfy HART physical layer requirements including modulation, demodulation, receive filtering, carrier detect, and transmit−signal shaping. In addition, the NCN5192 also has an integrated DAC for low-BOM current loop slave transmitter implementation. The NCN5192 uses phase continuous frequency shift keying (FSK) at 1200 bits per second. To conserve power the receive circuits are disabled during transmit operations and vice versa. This provides the half−duplex operation used in HART communications. Features • Single−chip, Half−duplex 1200 Bits per Second FSK Modem • Bell 202 Shift Frequencies of 1200 Hz and 2200 Hz • 3.0 V − 5.5 V Power Supply • Transmit−signal Wave Shaping • Receive Band−pass Filter • Low Power: Optimal for Intrinsically Safe Applications • Compatible with 3.3 V or 5 V Microcontroller • Internal Oscillator Requires 460.8 kHz, 920 kHz or 1.8 MHz Crystal or Ceramic Resonator • SPI Communication • Integrated 16 bit Sigma-Delta DAC • Meets HART Physical Layer Requirements • Industrial Temperature Range of −40°C to +85°C • Available in 32−pin NQFP Package • These are Pb−Free Devices Applications • HART Multiplexers • HART Modem Interfaces • 4 − 20 mA Loop Powered Transmitters http://onsemi.com MARKING DIAGRAM 1 32 QFN32 CASE 488AM 1 NCN 5192 AWLYYWW G NCN5192 = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. © Semiconductor Components Industries, LLC, 2014 February, 2014 − Rev. 3 1 Publication Order Number: NCN5192/D 1 page POWER 3.0 to 5.5 V mC 1. 8 MHz RESET VPOR KICK RxD_ENH RxD CD TxD RTS CS DATA CLK CLK1 CLK2 XOUT XIN NCN5192 TYPICAL APPLICATION VDD VDDA RxAFI RxAF RxA HART IN NCN5192 CBIAS VSS VSSA AREF VDDA LM285 CDREF TxA DAC JUMP DACREF S VDDA HART & 4 – 20 mA OUT Figure 2. Application Diagram NCN5192 http://onsemi.com 5 5 Page NCN5192 clock frequency of 460.8 kHz. CS is clocked in at the falling edge of the CLK1 clock to detect if the data is for the mode register or the DAC. SCLK can begin to clock in DATA serially to the chip on the falling edge of SCLK. SCLK should have a maximum frequency of 460.8 kHz. The format of the data should be either 8 or 16 bits with the most significant bit first. DATA is shifted into the chip on the falling edge of SCLK, and thus for correct operation DATA should change only on the rising edge of SCLK. The first bit shifted in is the MSB. If 14 bit DAC communication is utilized, then two 0’s should precede the 14 bits, and 16 clock cycles on SCLK should occur. Once the data is shifted in, CS should go low no sooner than one clock cycle after the last rising edge of SCLK. Table 9. INTERNAL REGISTER DESCRIPTION Bit Description 0 (LSB) 0 = DAC in 14−bit mode 1 = DAC in 16−bit mode 1 Set the crystal divide so that CLK2 is 460.8 kHz Bit 2 Bit 1 0 0 Crystal/2 2 0 1 Crystal/4 1 0 Crystal/1 1 1 Crystal/4 3 Set the crystal divide for CLK1 Bit 4 Bit 3 0 0 Crystal/2 4 0 1 Crystal/4 1 0 Crystal/1 1 1 Crystal/4 5 0 = Watchdog kick external (pin) 1 = Watchdog kick internal (1.8 kHz) 6 0 = RTZ output format on DAC 1 = Non RTZ output format on DAC 7 (MSB) 0 = RxD is low when carrier is off 1 = RxD is high when carrier is off Setting this bit, changes the function of RxD to the function of RxD_ENH Internal Register The NCN5192 has an 8 bit register to setup its internal operation. An 8 bit SPI communication method is used to write to the mode register. If CS goes low after only 8 clock cycles of SCLK the Mode register will latch in the 8 bits which are shifted into the SPI shift register. In Table 9 an explanation of the usage of each bit is given. All bits are set to ‘0’ at reset. Sigma Delta DAC The NCN5192 Modem has an integrated Sigma−Delta Modulator for use in a current loop slave transmitter. Through this DAC, an analog value can be set and transmitted across the current loop. For more information on how to create a current loop slave transmitter, see application notes on the ON Semi website. The DAC output will switch between 0 V and the voltage provided to DACREF. To achieve maximum accuracy, the DACREF voltage should be kept stable, so that power supply variations are not visible in the DAC output. The Sigma−Delta modulator output can be set through SPI frames containing 14 or 16 significant bits. The length of the data frames can be set through bit 0 is the status register. The output of the DAC can be set return to zero (RTZ) or non−RTZ. This is important when the rise and fall time of the signal are not identical. This will cause a DC offset depending on the number of rising and falling edges. As the output bits of a sigma−delta modulator are randomly arranged (ie. for the same setting we could get 01110000 or 01010100), the number of edges might vary over time for a non return to zero signal. Setting the DAC to “return to zero” forces the output to have a rising and falling edge for each logic “1” bit, so that no offset from pulse asymmetry can occur. However, this will decrease the range of the modulator to 50% of DACREF, as the maximum duty cycle is 50% instead of 100% for NRZ. When a clock failure is detected, using an internal oscillator, the DAC output will jump to the level set by the JUMP pin, until the IC is reset or a rising flank is detected on KICK. Table 10. SPI FRAME FORMAT Description Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register 8 Mode Register Data DAC – 14 bits mode 16 0 0 DAC Output Word DAC – 16 bits mode 16 DAC Output Word http://onsemi.com 11 11 Page

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