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PDF UPD3140GS Data sheet ( Hoja de datos )

Número de pieza UPD3140GS
Descripción DUAL PLL FREQUENCY SYNTHESIZER LSI
Fabricantes NEC 
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DATA SHEET
BiCMOS INTEGRATED CIRCUIT
µPD3140GS
1.8 to 5.5 V BIAS, 80 MHz to 550 MHz DUAL PLL FREQUENCY SYNTHESIZER
LSI FOR CORDLESS TELEPHONES AND PORTABLE CELLULAR RADIO
DESCRIPTION
µPD3140GS is a dual PLL frequency synthesizer LSI designed for cordless telephones and portable cellular radio. This
LSI is manufactured using 13 GHz fT BiCMOS process and integrated 2 pairs of prescaler + PLL operate from 80 MHz to
550 MHz. This LSI realizes low power consumption: on 1.8 V, 4.3 mA at dual operation and 2.7 mA at single operation. The
additional functions are high-speed lockup and lock phase sensitivity setting. The package is a 20-pin SSOP (300 mil) suitable
for high-density surface mounting. Thus, this product contributes to produce physically-small, low power-consumption, long-
life battery systems.
FEATURES
• Supply voltage: VCC1 = VCC2 = 1.8 to 5.5 V
• Input operating frequency: fin = 80 MHz to 550 MHz (PLL 1ch, 2ch in common)
• Reference oscillating frequency fref = 30 MHz MAX.. Built-in high-speed reference oscillator signal can be taken out from the
buffer amplifier output pin.
• Built-in power-save function: control 2 prescaler’s ON/OFF operation individually.
• Low power consumption: Dual operation (both ch ON): ICC OP2 = 4.3 mA TYP. @ VCC = 1.8 V
Single operation (either ch ON): ICC OP1 = 2.7 mA TYP. @ VCC = 1.8 V
Power save mode (both ch OFF): ICC PS = 10 µA MAX. @ VCC = 1.8 V
• Decreased lockup time available: charge pump switch control (lockup time: 9 ms @ fstep = 12.5 kHz, 1 MHz swing, decreased
lockup time mode).
• Lock phase sensitivity programmable: Phase difference allowance for lock up can be controlled as 4 stages (150 ns to 5
µs).
• Pins and counter data are compatible to µPD2844BGS (except option data).
• High-density surface mounting: 20-pin plastic SSOP.
ORDERING INFORMATION
PARTS NUMBER
PACKAGE
SUPPLYING FORM
µPD3140GS-E1
µPD3140GS-E2
µPD3140GS-T1
20 pin plastic SSOP
(300 mil)
µPD3140GS-T2
Embossed tape 16 mm wide. QTY 2.5 k/reel
Pin1 is in tape pull-out direction.
Embossed tape 16 mm wide. QTY 2.5 k/reel
Pin1 is in tape roll-in direction.
Adhesive tape 32 mm wide. QTY 2 k/reel
Pin1 is in tape pull-out direction.
Adhesive tape 32 mm wide. QTY 2 k/reel
Pin1 is in tape roll-in direction.
* To order evaluation sample, please contact your local NEC sales office (Order number : µPD3140GS).
Caution: Electro-static sensitive device
Document No. P10957EJ2V0DS00 (2nd edition)
(Previous No. ID-3471)
Date Published April 1996 P
Printed in Japan
F©ree Datasheet http://www.d1a9ta9sh6eet4u.com/

1 page




UPD3140GS pdf
µPD3140GS
DATA FORMAT
ENABLE
DATA
A B D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
CLK
neglect
first bit
latchable
Note: Data can be clocked in at falling edge of the CLK.
Latest 19 bits data before EN:H L can be latched.
1. Relation between A, B data and setting data content
AB
Setting data content
0 0 PLL 1ch (2 pin input) N counter data
0 1 PLL 2ch (19 pin input) N counter data
1 0 Option data
1 1 Reference counter data (PLL 1ch, 2ch common)
last bit
Remarks: Stable operation against same N counter data latched.
2. Counter data
A, B = 0, 0 or 0, 1
PLL1ch, 2ch N counter Number : N = D17 × 216 + D16 × 215 + D15 × 214 + D14 × 213 + D13 × 212 + D12 × 211 + D11 ×
210 + D10 × 29 + D9 × 28 + D8 × 27 + D7 × 26 + D6 × 25 + D5 × 24 + D4 × 23 +
D3 × 22 + D2 × 21 + D1 × 20
Note: Continuous setting range = 4 096 to 131 071 (‘1’ should be set to any of D13 to D17 data.)
A, B = 1, 1
Reference Counter Number : R = D11 × 211 + D10 × 210 + D9 × 29 + D8 × 28 + D7 × 27 + D6 × 26 + D5 × 25 + D4 ×
24 + D3 × 23 + D2 × 22 + D1 × 21
Note: Setting range : 64 to 4 094 (Continuous even numbers can be set.)
3. Option settings (A, B = 1, 0)
<1> D1 to D6: Charge pump driving capability setting (CP data)
D3
(D6)
0
0
0
0
1
1
1
1
D2
(D5)
0
0
1
1
0
0
1
1
D1
(D4)
0
1
0
1
0
1
0
1
Charge pump driving capability
capability
Output
Current
Output
resistance Value
weak
10 µA
100 k
strong
30 µA
100 µA
130 µA
300 µA
330 µA
400 µA
Voltage output
33 k
10 k
7.7 k
3.3 k
3 k
2.5 k
0.5 k
1 Output resistance values are typical at
VCC = 2 V.
2 D1 to D3: PLL1ch data
D4 to D6: PLL2ch data
<2> D7: Charge pump polarity (PLL 1ch, 2ch common)
Input phase status against reference signal phase
D7 phase advanced phase delayed Sychronized
Filter Type
0 Low
High
High impedance Passive filter
1 High
Low High impedance Active filter
5
Free Datasheet http://www.datasheet4u.com/

5 Page





UPD3140GS arduino
2. AC measurement circuit
VCC1
10 000 pF
Serial data input
OUT
BNC
0.1 µF
To Frequency
Counter
4.7 µF
+
1 VCC1
2 IN1
3 EN
4 CLK
5 DATA
6 TEST
OPEN 7 LOK
OPEN 8 CP1
OPEN 9 FI1
OPEN 10 FO1
µPD3140GS
GND1 20
IN2 19
VCC2 18
4.7 µF
+
XB 17 OPEN
XI 16 OPEN
XO 15 OPEN
GND2 14
CP2 13 OPEN
FI2 12 OPEN
FO2 11 OPEN
10 000 pF
10 000 pF
51
VCC2
10 000 pF
IN
BNC
From SG
Input response of internal prescaler measurement flow.
1. Supply power (VCC1, VCC2 ON).
2. Serial data input to 3, 4, and 5 pin.
[Command as dual operation with option data D8 and D9.]
3. Set TEST mode.
VCC2 = VCC1 + 2 (Other bias = VCC1)
4. The 1ch (IN1) or 2ch (IN2) prescaler output can be monitored at TEST pin. (See the table below.)
EN (3 pin) input
H
L
DATA (5 pin) input
L
H
TEST (6 pin)
1ch prescaler output
2ch prescaler output
11
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