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PDF MAX1215 Data sheet ( Hoja de datos )
| Número de pieza | MAX1215 | |
| Descripción | 250Msps ADC | |
| Fabricantes | Maxim Integrated | |
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19-3653; Rev 1; 9/06
EVAALVUAAILTAIOBNLEKIT
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
General Description
The MAX1215 is a monolithic, 12-bit, 250Msps analog-
to-digital converter (ADC) optimized for outstanding
dynamic performance at high-IF frequencies up to
300MHz. The product operates with conversion rates
up to 250Msps while consuming only 975mW.
At 250Msps and an input frequency up to 250MHz, the
MAX1215 achieves a spurious-free dynamic range
(SFDR) of 72.4dBc. Its excellent signal-to-noise ratio
(SNR) of 66dB at 10MHz remains flat (within 2dB) for
input tones up to 300MHz. This ADC yields an excellent
low noise floor of -67.5dBFS, which makes it ideal for
wideband applications such as cable-head end
receivers and power-amplifier predistortion in cellular
base-station transceivers.
The MAX1215 requires a single 1.8V supply. The analog
input is designed for either differential or single-ended
operation and can be AC- or DC-coupled. The ADC also
features a selectable on-chip divide-by-2 clock circuit,
which allows the user to apply clock frequencies as high
as 340MHz. This helps to reduce the phase noise of the
input clock source. A low-voltage differential signal
(LVDS) sampling clock is recommended for best perfor-
mance. The converter’s digital outputs are LVDS com-
patible and the data format can be selected to be either
two’s complement or offset binary.
The MAX1215 is available in a 68-pin QFN package
with exposed paddle (EP) and is specified over the
industrial (-40°C to +85°C) temperature range.
See the Pin-Compatible Versions table for a complete
selection of 8-bit, 10-bit, and 12-bit high-speed ADCs in
this family (with or without input buffers).
Applications
Base-Station Power-Amplifier Linearization
Cable-Head End Receivers
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
Pin Configuration appears at end of data sheet.
Features
♦ 250Msps Conversion Rate
♦ Low Noise Floor of -67.5dBFS
♦ Excellent Low-Noise Characteristics
SNR = 65.5dB at fIN = 100MHz
SNR = 65dB at fIN = 250MHz
♦ Excellent Dynamic Range
SFDR = 70.7dBc at fIN = 100MHz
SFDR = 72.4dBc at fIN = 250MHz
♦ 65.4dB NPR for fNOTCH = 28.8MHz and a Noise
Bandwidth of 50MHz
♦ Single 1.8V Supply
♦ 1006mW Power Dissipation at fSAMPLE = 250MHz
and fIN = 100MHz
♦ On-Chip Track-and-Hold Amplifier
♦ Internal 1.24V-Bandgap Reference
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ LVDS Digital Outputs with Data Clock Output
♦ MAX1215 EV Kit Available
Ordering Information
PART
TEMP RANGE
MAX1215EGK-D
-40°C to +85°C
MAX1215EGK+D -40°C to +85°C
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
PIN-PACKAGE
68 QFN-EP*
68 QFN-EP*
Pin-Compatible Versions
PART
MAX1121
MAX1122
MAX1123
MAX1124
MAX1213
MAX1214
MAX1215
MAX1213N
MAX1214N
MAX1215N
RESOLUTION
(BITS)
8
10
10
10
12
12
12
12
12
12
SPEED GRADE
(Msps)
250
170
210
250
170
210
250
170
210
250
ON-CHIP
BUFFER
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Free Datasheet http://www.datasheet4u.com/
1 page  
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
Typical Operating Characteristics
(AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, AIN = -1dBFS; see each TOC for detailed information on test condi-
tions, differential input drive, differential sine-wave clock input drive, 0.1µF capacitor on REFIO, internal reference, digital output pins
differential RL = 100Ω, TA = +25°C.)
FFT PLOT
(8192-POINT DATA RECORD)
FFT PLOT
(8192-POINT DATA RECORD)
FFT PLOT
(8192-POINT DATA RECORD)
0
-10
fSAMPLE =
249.99936MHz
0
fSAMPLE =
-10 249.99936MHz
-20
-30
fIN = 12.78683MHz
AIN = -1.008dBFS
SNR = 66.5dB
-20 fIN = 65.03279MHz
-30
AIN = -1.083dBFS
SNR = 66.7dB
-40
SINAD = 66.2dB
-40 SINAD = 65.6dB
-50
-60
THD = -80.4dBc
SFDR = 83.3dBc
HD2 = -83.3dBc
-50 THD = -72dBc
SFDR = 73.7dBc
-60 HD2 = -82dBc
-70 HD2 HD3 = -88.4dBc
-70 HD3 = -73.7dBc
HD3
-80
-80 HD3
HD2
0
-10
-20
-30
-40
-50
-60
-70
-80
fSAMPLE =
249.99936MHz
fIN = 199.24876MHz
AIN = -1.018dBFS
SNR = 65.5dB
SINAD = 63.2dB
THD = -67dBc
SFDR = 67.1dBc
HD2 = -89.1dBc
HD3
HD3 = -67.1dBc
HD2
-90 -90 -90
-100 -100 -100
-110
0
20 40 60 80 100 120
ANALOG INPUT FREQUENCY (MHz)
-110
0
20 40 60 80 100 120
ANALOG INPUT FREQUENCY (MHz)
-110
0
20 40 60 80 100 120
ANALOG INPUT FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
FFT PLOT
(8192-POINT DATA RECORD)
fSAMPLE =
249.99936MHz
fIN fIN = 248.62607MHz
AIN = -1.059dBFS
SNR = 65dB
SINAD = 64.2dB
THD = -71.5dBc
HD3 SFDR = 72.4dBc
HD2 = -82.1dBc
HD3 = -72.4dBc
HD2
20 40 60 80 100 120
ANALOG INPUT FREQUENCY (MHz)
TWO-TONE IMD PLOT
(8192-POINT DATA RECORD)
0
-10
fSAMPLE = 249.99936MHz
fIN1 = 99.21239MHz
-20 fIN2 = 101.1044775MHz
-30
AIN1 = AIN2 = -7dBFS
IMD = -79dBc
-40
fIN1
fIN2
-50
-60
-70 2fIN2 - fIN1
-80 2fIN1 - fIN2
-90
-100
-110
0
20 40 60 80 100 120
ANALOG INPUT FREQUENCY (MHz)
SNR/SINAD vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 249.99936MHz, AIN = -1dBFS)
70
SNR
67
64
SINAD
61
58
55
0
50 100 150 200 250 300
fIN (MHz)
SFDR vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 249.99936MHz, AIN = -1dBFS)
90
85
80
75
70
65
60
55
50
45
40
0
50 100 150 200 250 300
fIN (MHz)
HD2/HD3 vs. ANALOG INPUT FREQUENCY
(fSAMPLE = 249.99936MHz, AIN = -1dBFS)
-60
-65 HD3
-70
-75
-80
-85
-90
HD2
-95
-100
0
50 100 150 200 250 300
fIN (MHz)
SNR/SINAD vs. ANALOG INPUT AMPLITUDE
(fSAMPLE = 249.99936MHz, fIN = 65.03279MHz)
70
60 SNR
50
SINAD
40
30
20
10
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0
ANALOG INPUT AMPLITUDE (dBFS)
_______________________________________________________________________________________ 5
Free Datasheet http://www.datasheet4u.com/
5 Page 
1.8V, 12-Bit, 250Msps ADC for
Broadband Applications
On-Chip Reference Circuit
The MAX1215 features an internal 1.23V bandgap refer-
ence circuit (Figure 3), which in combination with an inter-
nal reference-scaling amplifier determines the FSR of the
MAX1215. Bypass REFIO with a 0.1µF capacitor to
AGND. To compensate for gain errors or increase the
ADC’s FSR, the voltage of this bandgap reference can be
indirectly adjusted by adding an external resistor (e.g.,
100kΩ trim potentiometer) between REFADJ and AGND
or REFADJ and REFIO. See the Applications Information
section for a detailed description of this process.
To disable the internal reference, connect REFADJ to
AVCC. In this configuration, an external, stable refer-
ence must be applied to REFIO to set the converter’s
full scale. To enable the internal reference, connect
REFADJ to AGND.
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1215
with an LVDS- or LVPECL-compatible clock to achieve
the best dynamic performance. The clock signal source
must be a high-quality, low phase noise with fast edge
rates to avoid any degradation in the noise performance
of the ADC. The clock inputs (CLKP, CLKN) are internally
biased to 1.15V, accept a typical 0.5VP-P differential sig-
nal swing, and are usually driven in AC-coupled configu-
ration. See the Differential, AC-Coupled PECL-
Compatible Clock Input section for more circuit details
on how to drive CLKP and CLKN appropriately. Although
not recommended, the clock inputs also accept a single-
ended input signal.
The MAX1215 also features an internal clock-manage-
ment circuit (duty-cycle equalizer) that ensures the
clock signal applied to inputs CLKP and CLKN is
processed to provide a 50% duty-cycle clock signal
that desensitizes the performance of the converter to
variations in the duty cycle of the input clock source.
Note that the clock duty-cycle equalizer cannot be
turned off externally and requires a minimum clock fre-
quency of > 20MHz to work appropriately and accord-
ing to data sheet specifications.
Data Clock Outputs (DCLKP, DCLKN)
The MAX1215 features a differential clock output, which
can be used to latch the digital output data with an
external latch or receiver. Additionally, the clock output
can be used to synchronize external devices (e.g.,
FPGAs) to the ADC. DCLKP and DCLKN are differential
outputs with LVDS-compatible voltage levels. There is a
3.87ns delay time between the rising (falling) edge of
CLKP (CLKN) and the rising edge of DCLKP (DCLKN).
See Figure 4 for timing details.
Divide-by-2 Clock Control (CLKDIV)
The MAX1215 offers a clock control line (CLKDIV),
which supports the reduction of clock jitter in a system.
Connect CLKDIV to OGND to enable the ADC’s internal
divide-by-2 clock divider. Data is now updated at one-
half the ADC’s input clock rate. CLKDIV has an internal
pulldown resistor and can be left open for applications
that require this divide-by-2 mode. Connecting CLKDIV
to OVCC disables the divide-by-2 mode.
ADC FULL SCALE = REFT - REFB
REFERENCE
1V BUFFER
REFT REFERENCE
SCALING AMPLIFIER
G
REFB
REFIO
0.1μF
CONTROL LINE TO
DISABLE REFERENCE BUFFER
REFADJ
100Ω*
REFT: TOP OF REFERENCE LADDER.
REFB: BOTTOM OF REFERENCE LADDER.
AVCC
AVCC/2
MAX1215
*REFADJ MAY
BE SHORTED TO
AGND DIRECTLY
Figure 3. Simplified Reference Architecture
______________________________________________________________________________________ 11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MAX1215.PDF ] | |
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