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PDF IR3876MPBF Data sheet ( Hoja de datos )
| Número de pieza | IR3876MPBF | |
| Descripción | SYNCHRONOUS BUCK REGULATOR | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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PD-97763
IR3876MPBF
SupIRBuckTM
12A HIGHLY INTEGRATED
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
Input Voltage Range: 3V to 21V
Output Voltage Range: 0.5V to 12V
Continuous 12A Load Capability
Constant On-Time control
Excellent Efficiency at very low output current levels
Compensation Loop not Required
Programmable switching frequency, soft start, and
over current protection
Power Good Output
Precision Voltage Reference (0.5V, +/-1%)
Pre-bias Start Up
Under/Over Voltage Fault Protection
Ultra small, low profile 5mm x 6mm QFN Package
Applications
Notebook and desktop computers
Game consoles
Consumer electronics – STB, LCD, TV, printers
General purpose POL DC-DC converters
Description
The IR3876 SupIRBuckTM is an easy-to-use,
fully integrated and highly efficient DC/DC
voltage regulator. The onboard constant on time
hysteretic controller and MOSFETs make
IR3876 a space-efficient solution that delivers up
to 12A of precisely controlled output voltage in
60oC ambient temperature applications without
airflow.
Programmable switching frequency, soft start,
and over current protection allows for a very
flexible solution suitable for many different
applications and an ideal choice for battery
powered applications.
Additional features include pre-bias startup, very
precise 0.5V reference, over/under voltage shut
down, power good output, and enable input with
voltage monitoring capability.
V5
(4.5V-7.5 V)
RFF
VIN
(3V-21V)
CLDO
CSS
VCC
3VCBP
FF
VIN BOOT
PHASE
EN IR 3876
PGND
PGOOD
SS
GND
ISET
FB
CBOOT
L
RISET
VOUT
(0.5V-12V)
C0
R1
R2
1
Free Datasheet http://www.datasheet4u.com/
1 page  
Recommended Operating Conditions
IR3876MPBF
Symbol
VIN
VCC
VOUT
IOUT
Fs
TJ
Definition
Input Voltage
Supply Voltage
Output Voltage
Output Current
Switching Frequency
Junction Temperature
Min
3
4.5
0.5
0
N/A
0
Max
21*
7.5
12
12
1000
125
Unit
V
A
kHz
oC
* Note: PHASE pin must not exceed 25V.
Electrical Specifications
Unless otherwise specified, these specification apply over VIN = 12V, VCC = 5V, 0oC ≤ TJ ≤ 125oC.
PARAMETER
BIAS SUPPLIES
VCC Turn-on Threshold
VCC Turn-off Threshold
VCC Threshold Hysteresis
VCC Operating Current
NOTE
VCC Shutdown Current
FF Shutdown Current
VIN Shutdown Current
INTERNAL LDO OUTPUT
LDO Output Voltage Range
Output Current
CONTROL LOOP
Reference Accuracy, VREF
On-Time Accuracy
Min Off Time
Soft-Start Current
Zero Current Threshold
FAULT PROTECTION
ISET Pin Output Current
Under Voltage Threshold
Under Voltage Hysteresis
Over Voltage Threshold
Over Voltage Hysteresis
PGOOD Delay Threshold
(VSS)
1
1
1
1
TEST CONDITION
RFF = 200K,
EN = HIGH, Fs = 300kHz
EN = LOW
EN = LOW
EN = LOW
CLDO = 1µF
VREF
RFF = 180K, TJ = 65oC
EN = HIGH
Measure at VPHASE
Falling VFB & Monitor PGOOD
Rising VFB
Rising VFB & Monitor PGOOD
Falling VFB
MIN TYP MAX UNIT
3.9 4.2 4.5
3.6 3.9 4.2
150
9.2
V
V
mV
mA
35 50 µA
2 µA
1 µA
3.1 3.3 3.5 V
8 mA
0.495 0.5 0.505
280 300 320
400
8 10 12
-5 -2.4 0
V
ns
ns
µA
mV
18 20 22
0.37 0.4 0.43
10
0.58 0.62 0.66
10
1
µA
V
mV
V
mV
V
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
CIRCUIT DESCRIPTION
PWM COMPARATOR
The PWM comparator initiates a SET signal
(PWM pulse) when the FB pin falls below the
reference (Vref) or the soft start (SS) voltage.
ON-TIME GENERATOR
The PWM on-time duration is programmed with
an external resistor (RFF) from the input supply
(VIN) to the FF pin. The simplified calculation for
RFF is shown in equation 1. The FF pin is held to
an internal reference after EN goes HIGH. A copy
of the current in RFF charges a timing capacitor,
which sets the on-time duration, as shown in
equation 2.
RFF
VOUT
(1)
1V 20 pF FSW
TON RFF 1V 20 pF (2)
VIN
CONTROL LOGIC
The control logic monitors input power sources,
sequences the converter through the soft-start
and protective modes, and initiates an internal
RUN signal when all conditions are met.
VCC and 3VCBP pins are continuously monitored,
and the IR3876 will be disabled if the voltage of
either pin drops below the falling thresholds.
EN_DELAY will become HIGH when VCC and
3VCBP are in the normal operating range and the
EN pin = HIGH.
SOFT START
With EN = HIGH, an internal 10µA current source
charges the external capacitor (CSS) on the SS pin
to set the output voltage slew rate during the soft
start interval. The soft start time (tSS) can be
calculated from equation 3.
t SS
CSS 0.5V
10A
(3)
The feedback voltage tracks the SS pin until SS
reaches the 0.5V reference voltage (Vref), then
feedback is regulated to Vref. CSS will continue to
be charged, and when SS pin reaches VSS (see
Electrical Specification), SS_DELAY goes HIGH.
With EN_DELAY = LOW, the capacitor voltage
and SS pin is held to the FB pin voltage. A normal
startup sequence is shown in Figure 17.
IR3876MPBF
PGOOD
The PGOOD pin is open drain and it needs to
be externally pulled high. High state indicates
that output is in regulation. The PGOOD logic
monitors EN_DELAY, SS_DELAY, and
under/over voltage fault signals. PGOOD is
released only when EN_DELAY and
SS_DELAY = HIGH and output voltage is within
the OV and UV thresholds.
PRE-BIAS STARTUP
IR3876 is able to start up into pre-charged
output, which prevents oscillation and
disturbances of the output voltage.
With constant on-time control, the output
voltage is compared with the soft start voltage
(SS) or Vref, depending on which one is lower,
and will not start switching unless the output
voltage drops below the reference. This scheme
prevents discharge of a pre-biased output
voltage.
SHUTDOWN
The IR3876 will shutdown if VCC is below its
UVLO limit. The IR3876 can be shutdown by
pulling the EN pin below its lower threshold.
Alternatively, the output can be shutdown by
pulling the soft start pin below 0.3V.
Figure 17. Normal Startup
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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