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PDF IR3865MPBF Data sheet ( Hoja de datos )
| Número de pieza | IR3865MPBF | |
| Descripción | SYNCHRONOUS BUCK REGULATOR | |
| Fabricantes | International Rectifier | |
| Logotipo |  |
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PD-97606
IR3865MPBF
SupIRBuckTM
10A HIGHLY INTEGRATED
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
Input Voltage Range: 3V to 21V
Output Voltage Range: 0.5V to 12V
Continuous 10A Load Capability
Constant On-Time Control
Compensation Loop not Required
Excellent Efficiency at Very Low Output Currents
Programmable Switching Frequency and Soft
Start
Thermally Compensated Over Current
Protection
Power Good Output
Precision Voltage Reference (0.5V, +/-1%)
Enable Input with Voltage Monitoring Capability
Pre-bias Start Up
Thermal Shut Down
Under/Over Voltage Fault Protection
Forced Continuous Conduction Mode Option
Very Small, Low Profile 4mm x 5mm QFN
Package
Description
The IR3865 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC voltage
regulator. The onboard constant on-time
hysteretic controller and MOSFETs make IR3865
a space-efficient solution that delivers up to 10A
of precisely controlled output voltage.
Programmable switching frequency, soft start,
and thermally compensated over current
protection allows for a very flexible solution
suitable for many different applications and an
ideal choice for battery powered applications.
Additional features include pre-bias startup, very
precise 0.5V reference, over/under voltage shut
down, power good output, and enable input with
voltage monitoring capability.
Applications
Notebook and Desktop Computers
Game Consoles
Consumer Electronics – STB, LCD, TV, Printers
General Purpose POL DC-DC Converters
8/8/2012 Rev3.1
1
Free Datasheet http://www.datasheet4u.com/
1 page  
Recommended Operating Conditions
Symbol
VIN
VCC
VOUT
IOUT
Fs
TJ
Definition
Input Voltage
Supply Voltage
Output Voltage
Output Current
Switching Frequency
Junction Temperature
* PHASE pin must not exceed 25V.
Min
3
4.5
0.5
0
N/A
-40
IR3865MPBF
Max
21*
5.5
12
10
750
125
Unit
V
A
kHz
oC
Electrical Specifications
Unless otherwise specified, these specification apply over VIN = 12V, 4.5V<VCC<5.5V, 0oC ≤ TJ ≤ 125oC.
PARAMETER
NOTE
TEST CONDITION
CONTROL LOOP
Reference Accuracy, VREF
On-Time Accuracy
Min Off Time
VFB = 0.5V
RFF = 180K, TJ = 65oC
Soft-Start Current
EN = High
DCM Comparator Offset
SUPPLY CURRENT
Measure at VPHASE
VCC Supply Current
(standby)
EN = Low, No Switching
VCC Supply Current
(dynamic)
EN = High, Fs = 300kHz
FF Shutdown Current
EN = Low
FORCED CONTINUOUS CONDUCTION MODE (FCCM)
FCCM Start Threshold
FCCM Stop Threshold
MIN TYP MAX UNIT
0.495 0.5 0.505
280 300 320
500
8 10 12
-4.5 -2.5 0
V
ns
ns
µA
mV
23 µA
7 mA
2 µA
2V
0.6 V
8/8/2012 Rev3.1
5
Free Datasheet http://www.datasheet4u.com/
5 Page 
CIRCUIT DESCRIPTION
PWM COMPARATOR
The PWM comparator initiates a SET signal
(PWM pulse) when the FB pin falls below the
reference (VREF) or the soft start (SS) voltage.
ON-TIME GENERATOR
The PWM on-time duration is programmed with
an external resistor (RFF) from the input supply
(VIN) to the FF pin. The simplified equation for
RFF is shown in equation 1. The FF pin is held
to an internal reference after EN goes HIGH. A
copy of the current in RFF charges a timing
capacitor, which sets the on-time duration, as
shown in equation 2.
RFF
VOUT
(1)
1V 20 pF FSW
TON RFF 1V 20 pF (2)
VIN
CONTROL LOGIC
The control logic monitors input power sources,
sequences the converter through the soft-start
and protective modes, and initiates an internal
RUN signal when all conditions are met.
VCC and 3VCBP pins are continuously
monitored, and the IR3865 will be disabled if the
voltage of either pin drops below the falling
thresholds. EN_DELAY will become HIGH when
VCC and 3VCBP are in the normal operating
range and the EN pin = HIGH.
SOFT START
With EN = HIGH, an internal 10µA current
source charges the external capacitor (CSS) on
the SS pin to set the output voltage slew rate
during the soft start interval. The soft start time
(tSS) can be calculated from equation 3.
tSS
CSS 0.5V
10A
(3)
The feedback voltage tracks the SS pin until SS
reaches the 0.5V reference voltage (Vref), then
feedback is regulated to Vref. CSS will continue
to be charged, and when SS pin reaches VSS
(see Electrical Specification), SS_DELAY goes
HIGH. With EN_DELAY = LOW, the capacitor
voltage and SS pin is held to the FB pin voltage.
A normal startup sequence is shown in Figure
20.
8/8/2012 Rev3.1
IR3865MPBF
PGOOD
The PGOOD pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation. The PGOOD logic monitors
EN_DELAY, SS_DELAY, and under/over voltage
fault signals. PGOOD is released only when
EN_DELAY and SS_DELAY = HIGH and output
voltage is within the OV and UV thresholds.
PRE-BIAS STARTUP
IR3865 is able to start up into pre-charged output,
which prevents oscillation and disturbances of the
output voltage.
With constant on-time control, the output voltage
is compared with the soft start voltage (SS) or
Vref, depending on which one is lower, and will
not start switching unless the output voltage drops
below the reference. This scheme prevents
discharge of a pre-biased output voltage.
SHUTDOWN
The IR3865 will shutdown if VCC is below its
UVLO limit. The IR3865 can be shutdown by
pulling the EN pin below its lower threshold.
Alternatively, the output can be shutdown by
pulling the soft start pin below 0.3V.
Figure 20. Normal Startup
11
Free Datasheet http://www.datasheet4u.com/
11 Page | ||
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| PDF Descargar | [ Datasheet IR3865MPBF.PDF ] | |
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