23LC1024 Datasheet PDF - Microchip
| Part Number | 23LC1024 | |
| Description | 1Mbit SPI Serial SRAM | |
| Manufacturers | Microchip | |
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23A1024/23LC1024
1Mbit SPI Serial SRAM with SDI and SQI Interface
Device Selection Table
Part
Number
VCC Range
23A1024
1.7-2.2V
23LC1024
2.5-5.5V
Note 1: 16 MHz for E-temp.
Temp.
Ranges
I, E
I, E
Dual I/O
(SDI)
Yes
Yes
Quad I/O
(SQI)
Yes
Yes
Max. Clock
Frequency
20 MHz(1)
20 MHz(1)
Packages
SN, ST, P
SN, ST, P
Features
• SPI Bus Interface:
- SPI compatible
- SDI (dual) and SQI (quad) compatible
- 20 MHz Clock rate for all modes
• Low-Power CMOS Technology:
- Read Current: 3 mA at 5.5V, 20 MHz
- Standby Current: 4 A at +85°C
• Unlimited Read and Write Cycles
• Zero Write Time
• 128K x 8-bit Organization:
- 32-byte page
• Byte, Page and Sequential Mode for Reads and
Writes
• High Reliability
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
- Automotive (E): -40C to +125C
• RoHS Compliant
• 8 Lead SOIC, TSSOP and PDIP Packages
Pin Function Table
Name
Function
CS
SO/SIO1
SIO2
VSS
SI/SIO0
SCK
HOLD/SIO3
VCC
Chip Select Input Pin
Serial Output/SDI/SQI Pin
SQI Pin
Ground Pin
Serial Input/SDI/SQI Pin
Serial Clock Pin
Hold/SQI Pin
Power Supply Pin
Description
The Microchip Technology Inc. 23A1024/23LC1024
are 1 Mbit Serial SRAM devices. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK), a data in line (SI) and a data out line
(SO). Access to the device is controlled through a Chip
Select (CS) input. Additionally, SDI (Serial Dual
Interface) and SQI (Serial Quad Interface) is supported
if your application needs faster data rates.
This device also supports unlimited reads and writes to
the memory array.
The 23A1024/23LC1024 is available in standard
packages including 8-lead SOIC, PDIP and advanced
8-lead TSSOP.
Package Types (not to scale)
SOIC/TSSOP/PDIP
CS 1
SO/SIO1
SIO2
2
3
VSS 4
8 VCC
7 HOLD/SIO3
6 SCK
5 SI/SIO0
2012-2015 Microchip Technology Inc.
DS20005142C-page 1
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2.0 FUNCTIONAL DESCRIPTION
2.1 Principles of Operation
The 23A1024/23LC1024 is an 1 Mbit Serial SRAM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
firmware to match the SPI protocol. In addition, the
23A1024/23LC1024 is capable of operation in SDI and
SQI modes. In SDI mode, the SI and SO data lines are
bidirectional, allowing the transfer of two bits per clock
pulse. In SQI mode, two additional data lines enable
the transfer of four bits per clock pulse.
The 23A1024/23LC1024 contains an 8-bit instruction
register. The device is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The
CS pin must be low for the entire operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
2.2 Modes of Operation
The 23X1024 has three modes of operation that are
selected by setting bits 7 and 6 in the MODE register.
The modes of operation are Byte, Page and Burst.
Byte Operation – is selected when bits 7 and 6 in the
MODE register are set to 00. In this mode, the
read/write operations are limited to only one byte. The
Command followed by the 24-bit address is clocked into
the device and the data to/from the device is transferred
on the next eight clocks (Figure 2-1, Figure 2-2).
Page Operation – is selected when bits 7 and 6 in the
MODE register are set to 10. The 23X1024 has
4096 pages of 32 bytes. In this mode, the read and write
operations are limited to within the addressed page (the
address is automatically incremented internally). If the
data being read or written reaches the page boundary,
then the internal address counter will increment to the
start of the page (Figure 2-3, Figure 2-4).
Sequential Operation – is selected when bits 7 and 6
in the MODE register are set to 01. Sequential
operation allows the entire array to be written to and
read from. The internal address counter is automatically
incremented and page boundaries are ignored. When
the internal address counter reaches the end of the
array, the address counter will roll over to 0x00000
(Figure 2-5, Figure 2-6).
23A1024/23LC1024
2.3 Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the
23A1024/23LC1024 followed by the 24-bit address,
with the first seven MSB’s of the address being “don’t
care” bits. After the correct READ instruction and
address are sent, the data stored in the memory at the
selected address is shifted out on the SO pin.
If operating in Sequential mode, the data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses. The internal
Address Pointer is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached (1FFFFh),
the address counter rolls over to address 00000h,
allowing the read cycle to be continued indefinitely.
The read operation is terminated by raising the CS
pin.
2.4 Write Sequence
Prior to any attempt to write data to the
23A1024/23LC1024, the device must be selected by
bringing CS low.
Once the device is selected, the Write command can
be started by issuing a WRITE instruction, followed by
the 24-bit address, with the first seven MSB’s of the
address being “don’t care” bits, and then the data to be
written. A write is terminated by the CS being brought
high.
If operating in Page mode, after the initial data byte is
shifted in, additional bytes can be shifted into the
device. The Address Pointer is automatically
incremented. This operation can continue for the entire
page (32 bytes) before data will start to be overwritten.
If operating in Sequential mode, after the initial data
byte is shifted in, additional bytes can be clocked into
the device. The internal Address Pointer is
automatically incremented. When the Address Pointer
reaches the highest address (1FFFFh), the address
counter rolls over to (00000h). This allows the
operation to continue indefinitely, however, previous
data will be overwritten.
2012-2015 Microchip Technology Inc.
DS20005142C-page 5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for 23LC1024 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ 23LC1024.PDF Datasheet ] | |
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