PDF HMT451S6MFR8C Data sheet ( Hoja de datos )

Número de pieza	HMT451S6MFR8C
Descripción	DDR3 SDRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! 204pin DDR3 SDRAM SODIMM DDR3 SDRAM Unbuffered SODIMMs Based on 4Gb M-die HMT425S6MFR6C HMT451S6MFR8C HMT41GS6MFR8C *SK hynix reserves the right to change products or specifications without notice. Rev. 1.0 /Jul. 2012 1 Free Datasheet http://www.datasheet4u.com/ 1 page Pin Descriptions Pin Name CK[1:0] CK[1:0] CKE[1:0] RAS CAS Description Clock Input, positive line Clock Input, negative line Clock Enables Row Address Strobe Column Address Strobe Num ber 2 2 2 1 1 WE Write Enable 1 S[1:0] A[9:0],A11, A[15:13] A10/AP A12/BC BA[2:0] ODT[1:0] SCL SDA SA[1:0] Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Addresses On Die Termination Inputs Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs 2 14 1 1 3 2 1 1 2 Pin Name DQ[63:0] DM[7:0] DQS[7:0] DQS[7:0] EVENT TEST RESET Description Num ber Data Input/Output 64 Data Masks 8 Data strobes 8 Data strobes, negative line 8 Temperature event pin 1 Logic Analyzer specific test pin (No connect on SODIMM) 1 Reset Pin 1 VDD Core and I/O Power 18 VSS Ground 52 VREFDQ VREFCA VTT VDDSPD NC Input/Output Reference Termination Voltage SPD Power Reserved for future use 1 1 2 1 2 Total: 204 Rev. 1.0 /Jul. 2012 5 Free Datasheet http://www.datasheet4u.com/ 5 Page 8GB, 1Gx64 Module(2Rank of x8) DQS3 DQS3 DM3 DQ[24:31] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D11 LDQS LDQS LDM DQ [0:7] 240ohm +/-1% ZQ D3 VDD Cterm Vtt VDD Cterm Vtt Vtt DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D4 DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D12 DQS4 DQS4 DM4 DQ[32:39] DQS1 DQS1 DM1 DQ[8:15] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D1 LDQS LDQS LDM DQ [0:7] 240ohm +/-1% ZQ D9 DQS DQS DM DQ [0:7] D14 240ohm +/-1% ZQ DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D6 DQS6 DQS6 DM6 DQ[48:55] DQS0 DQS0 DM0 DQ[0:7] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D0 LDQS LDQS LDM DQ [0:7] 240ohm +/-1% ZQ D8 DQS DQS DM DQ [0:7] D15 240ohm +/-1% ZQ DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D7 DQS7 DQS7 DM7 DQ[56:43] DQS2 DQS2 DM2 DQ[6:23] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D2 LDQS LDQS LDM DQ [0:7] 240ohm +/-1% ZQ D10 DQS DQS DM DQ [0:7] D13 240ohm +/-1% ZQ DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D5 DQS5 DQS5 DM5 DQ[40:47] The SPD may be integrated with the Temp SCL Sensor or may be SA0 a separate component SA1 SCL A0 A1 (SPD) A2 WP SDA V2 D9 D3 V3 V4 D8 D10 SCL SA0 SA1 SCL A0 A1 Temp Sensor (with SPD) A2 EVENT SDA V4 D0 D2 EVENT V1 8GB, 1Gx64 Module(2Rank of x8)NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS rela- Rank 0 V3 V2 D1 D11 tionships are maintained as shown Rank 1 V1 V9 V5 V5 Vtt V1 V9 V8 D12 D6 V7 V6 D5 D7 V6 D13 D15 V7 V8 D4 D14 Rev. 1.0 /Jul. 2012 Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0 CK1 CK0 CK1 CKE0 CKE1 S0 S1 ODT0 ODT1 EVENT RESET Vtt SPD/TS D0–D15 D0–D15 D0–D15 D0–D15, SPD, Temp sensor D0–D7 D8–D15 D0–D7 D8–D15 D0-D7 D8-D15 D0–D7 D8–D15 D0–D7 D8–D15 Temp Sensor D0-D15 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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