PDF HMT41GS6AFR8C Data sheet ( Hoja de datos )

Número de pieza	HMT41GS6AFR8C
Descripción	DDR3 SDRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! 204pin DDR3 SDRAM SODIMM DDR3 SDRAM Unbuffered SODIMMs Based on 4Gb A-die HMT425S6AFR6C HMT451S6AFR6C HMT451S6AFR8C HMT41GS6AFR8C *SK hynix reserves the right to change products or specifications without notice. Rev. 1.0 / Jul. 2013 1 Free Datasheet http://www.datasheet4u.com/ 1 page Pin Descriptions Pin Name CK[1:0] CK[1:0] CKE[1:0] RAS CAS Description Clock Input, positive line Clock Input, negative line Clock Enables Row Address Strobe Column Address Strobe Num ber 2 2 2 1 1 WE Write Enable 1 S[1:0] A[9:0],A11, A[15:13] A10/AP A12/BC BA[2:0] ODT[1:0] SCL SDA SA[1:0] Chip Selects Address Inputs Address Input/Autoprecharge Address Input/Burst chop SDRAM Bank Addresses On Die Termination Inputs Serial Presence Detect (SPD) Clock Input SPD Data Input/Output SPD Address Inputs 2 14 1 1 3 2 1 1 2 Pin Name DQ[63:0] DM[7:0] DQS[7:0] DQS[7:0] EVENT TEST RESET Description Num ber Data Input/Output 64 Data Masks 8 Data strobes 8 Data strobes, negative line 8 Temperature event pin 1 Logic Analyzer specific test pin (No connect on SODIMM) 1 Reset Pin 1 VDD Core and I/O Power 18 VSS Ground 52 VREFDQ VREFCA VTT VDDSPD NC Input/Output Reference Termination Voltage SPD Power Reserved for future use 1 1 2 1 2 Total: 204 Rev. 1.0 / Jul. 2013 5 Free Datasheet http://www.datasheet4u.com/ 5 Page 4GB, 512Mx64 Module(1Rank of x8) DQS0 DQS0 DM0 DQ[0:7] DQS2 DQS2 DM2 DQ[16:23] DQS4 DQS4 DM4 DQ[32:39] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D0 DQS1 DQS1 DM1 DQ[8:15] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D1 DQS3 DQS3 DM3 DQ[24:31] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D2 DQS5 DQS5 DM5 DQ[40:47] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ SCL SA0 SA1 SCL A0 A1 Temp Sensor (with SPD) A2 EVENT SDA D4 EVENT The SPD may be integrated with the Temp Sensor or may be a separate component SCL SCL SA0 SA1 A0 A1 (SPD) A2 WP SDA DQS DQS DM DQ [0:7] LDQS LDQS LDM DQ [0:7] 240ohm +/-1% ZQ D5 240ohm +/-1% ZQ D6 Vtt VDDSPD VREFCA VREFDQ VDD VSS CK0 CK0 CK1 CK1 S1 ODT1 CKE1 EVENT RESET Vtt SPD/TS D0–D7 D0–D7 D0–D7 D0–D7, SPD, Temp sensor D0–D7 D0–D7 Terminated near card edge NC NC NC Temp Sensor D0-D7 V1 D4 V2 D5 V3 V4 D6 D7 DQS6 DQS6 DM6 DQ[48:55] DQS DQS DM DQ [0:7] 240ohm +/-1% ZQ D3 DQS7 DQS7 DM7 DQ[56:63] LDQS LDQS LDM DQ [0:7] 240ohm +/-1% ZQ D7 V1 D0 V2 D1 V3 V4 D2 D3 Address and Control Lines NOTES 1. DQ wiring may differ from that shown however, DQ, DM, DQS, and DQS relationships are maintained as shown Rank 0 Rev. 1.0 / Jul. 2013 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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