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PDF HMT41GA7MFR8A Data sheet ( Hoja de datos )

Número de pieza HMT41GA7MFR8A
Descripción DDR3L SDRAM
Fabricantes Hynix Semiconductor 
Logotipo Hynix Semiconductor Logotipo



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No Preview Available ! HMT41GA7MFR8A Hoja de datos, Descripción, Manual

204pin DDR3L SDRAM ECC SODIMM
DDR3L SDRAM
ECC SO-DIMMs
Based on 4Gb M-die
HMT41GA7MFR8A
*SK hynix reserves the right to change products or specifications without notice.
Rev. 0.1 /Jul. 2012
1
Free Datasheet http://www.datasheet4u.com/

1 page




HMT41GA7MFR8A pdf
Pin Descriptions
Pin Name
Description
CK0
CK0
CK1
CK1
CKE[1:0]
RAS
CAS
WE
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Num
ber
1
1
1
1
2
1
1
1
S[3:0] Chip Selects
4
A[9:0],A11,
A[15:13]
Address Inputs
A10/AP Address Input/Autoprecharge
A12/BC Address Input/Burst chop
BA[2:0] SDRAM Bank Addresses
SCL
Serial Presence Detect (SPD) Clock
Input
SDA SPD Data Input/Output
SA[1:0] SPD Address Inputs
Par_In
Err_Out
Parity bit for the Address and Control
bus
Parity error found on the Address
and Control bus
14
1
1
3
1
1
2
1
1
Pin Name
Description
ODT[1:0]
DQ[63:0]
CB[7:0]
DQS[8:0]
DQS[8:0]
DM[8:0]
On Die Termination Inputs
Data Input/Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Data Masks
Num
ber
2
64
8
9
9
9
EVENT
Reserved for optional hardware
temperature event pin
1
RESET
VDD
VSS
VREFDQ
VREFCA
VTT
VDDSPD
Reset and SDRAM control pin
Power Supply
Ground
1
xx
xx
Reference Voltage for DQ
1
Reference Voltage for CA
Termination Voltage
1
2
SPD Power
1
Total : 204
Rev. 0.1 / Jul. 2012
5
Free Datasheet http://www.datasheet4u.com/

5 Page





HMT41GA7MFR8A arduino
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Symbol
Parameter
VDD
VDDQ
Notes:
Supply Voltage
Supply Voltage for Output
Min.
1.283
1.283
Rating
Typ.
1.35
1.35
Max.
1.45
1.45
Units
V
V
Notes
1,2,3,4
1,2,3,4
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3L specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - DDR3 (1.5V) operation
Symbol
Parameter
VDD
VDDQ
Notes:
Supply Voltage
Supply Voltage for Output
Min.
1.425
1.425
Rating
Typ.
1.5
1.5
Max.
1.575
1.575
Units
V
V
Notes
1,2,3
1,2,3
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 0.1 / Jul. 2012
11
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