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PDF AD9649 Data sheet ( Hoja de datos )
| Número de pieza | AD9649 | |
| Descripción | 1.8V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
14-Bit, 20/40/65/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9649
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
74.3 dBFS at 9.7 MHz input
71.5 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
87 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.35 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Integer 1, 2, or 4 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out (DCO) with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
RBIAS
VCM
VIN+
VIN–
VREF
SENSE
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND SDIO SCLK CSB DRVDD
SPI
PROGRAMMING DATA
ADC
CORE
OR
D13 (MSB)
D0 (LSB)
DCO
REF
SELECT
DIVIDE BY
1, 2, 4
AD9649
MODE
CONTROLS
CLK+ CLK–
PDWN DFS MODE
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD9649 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The sample-and-hold circuit maintains excellent performance
for input frequencies up to 200 MHz and is designed for low
cost, low power, and ease of use.
3. A standard serial port interface (SPI) supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO, data output
(D13 to D0) timing and offset adjustments, and voltage
reference modes.
4. The AD9649 is packaged in a 32-lead RoHS-compliant LFCSP
that is pin compatible with the AD9629 12-bit ADC and
the AD9609 10-bit ADC, enabling a simple migration path
between 10-bit and 14-bit converters sampling from 20 MSPS
to 80 MSPS.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9649
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance3
Input Common-Mode Voltage
Input Common-Mode Range
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input2 (DRVDD = 1.8 V)
Sine Wave Input2 (DRVDD = 3.3 V)
Standby Power4
Power-Down Power
Temp
Full
AD9649-20/AD9649-40
Min Typ
Max
14
Full Guaranteed
Full −0.40 +0.05
+0.50
Full −1.5
Full ±0.50
25°C ±0.25
Full ±1.30
25°C ±0.50
Full ±2
Full 0.984 0.996
Full 2
1.008
25°C 0.98
Full 2
Full 6
Full 0.9
Full 0.5
Full 7.5
1.3
Full 1.7 1.8
Full 1.7
1.9
3.6
Full 25.0/31.3 27.3/33.7
Full 1.6/2.9
Full 3.0/5.3
Full 45.2/57.2
Full 47.9/61.6 51.8/65.8
Full 54.9/73.8
Full 34/34
Full 0.5
AD9649-65
Min Typ Max
14
AD9649-80
Min Typ Max
14
Unit
Bits
Guaranteed
−0.40 +0.05 +0.50
−1.5
+0.55
±0.3
±1.30
±0.50
Guaranteed
−0.40 +0.05 +0.50
−1.5
±0.65
±0.35
±1.75
±0.60
% FSR
% FSR
LSB
LSB
LSB
LSB
±2 ±2 ppm/°C
0.984 0.996 1.008 0.984 0.996 1.008 V
2 2 mV
0.98 0.98 LSB rms
2 2 V p-p
6 6 pF
0.9 0.9 V
0.5 1.3 0.5 1.3 V
7.5 7.5 kΩ
1.7 1.8 1.9 1.7 1.8 1.9 V
1.7 3.6 1.7 3.6 V
41.0 44.0
4.7
8.4
47.0 50.0 mA
5.6 mA
10.2 mA
75.2
82.3
101.5
34
0.5
87.5
86.8
94.7
118.3
34
0.5
100
mW
mW
mW
mW
mW
1 Measured with 1.0 V external reference.
2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and ground.
4 Standby power is measured with a dc input and the CLK+, CLK− active.
Rev. A | Page 4 of 32
5 Page 
AD9649
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
CLK+ 1
CLK– 2
AVDD 3
CSB 4
SCLK/DFS 5
SDIO/PDWN 6
D0 (LSB) 7
D1 8
AD9649
TOP VIEW
(Not to Scale)
24 AVDD
23 MODE/OR
22 DCO
21 D13 (MSB)
20 D12
19 D11
18 D10
17 D9
NOTES
1. EXPOSED PADDLE. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION.
IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB
TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION,
NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
0
EPAD
Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog
ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength
benefits.
1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
3, 24, 29, 32
AVDD
1.8 V Supply Pin for the ADC CORE Domain.
4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
5
SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-down.
See Table 14 for details.
7 to 12, 14 to 21 D0 (LSB) to
D13 (MSB)
ADC Digital Outputs.
13
DRVDD
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22 DCO Data Clock Digital Output.
23
MODE/OR
Chip Mode Select Input in SPI Mode (MODE).
Out-of-Range Digital Output in SPI Mode or in Non-SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100).
Chip stand-by (SPI Register 0x08, Bits[7:5] = 101).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111).
In non-SPI mode, the pin operates only as an out-of-range (OR) digital output.
25
VREF
1.0 V Voltage Reference Input/Output. See Table 10.
26
SENSE
Reference Mode Selection. See Table 10.
27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28
RBIAS
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
30, 31
VIN−, VIN+ ADC Analog Inputs.
Rev. A | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9649.PDF ] | |
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