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PDF S70FL256P Data sheet ( Hoja de datos )
| Número de pieza | S70FL256P | |
| Descripción | 256-Mbit CMOS 3.0 Volt Flash Memory | |
| Fabricantes | SPANSION | |
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S70FL256P
256-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
S70FL256P Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S70FL256P_00
Revision 05
Issue Date January 30, 2013
1 page  
Data Sheet
Figures
Figure 2.1
Figure 2.2
Figure 9.1
Figure 10.1
16-pin Plastic Small Outline Package (SO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 x 8 mm 24-ball BGA Package, 5 x 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
January 30, 2013 S70FL256P_00_05
S70FL256P
5
5 Page 
Data Sheet
6. Device Operations
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Programming
Each Flash die must be programmed independently due to the nature of the dual die stack.
Simultaneous Die Operation
The user may only access one Flash die of the dual die stack at a time via its respective Chip Select.
Sequential Reads
Sequential reads are not supported across the end of the first Flash die to the beginning of the second. If the
user desires to sequentially read across the two die, data must be read out of the first die via CS1# and then
read out of the second die via CS2#.
Sector/Bulk Erase
A sector erase command must be issued for sectors in each Flash die separately. Full device Bulk Erase via
a single command is not supported due to the nature of the dual die stack. A Bulk Erase command must be
issued for each die.
Status Register
Each Flash die of the dual die stack is managed by its own Status Register. Reads and updates to the Status
Registers must be managed separately. It is recommended that Status Register control bit settings of each
die are kept identical to maintain consistency when switching between die.
Configuration Register
Each Flash die of the dual die stack is managed by its own Configuration Register. Updates to the
Configuration Register control bits must be managed separately. It is recommended that Configuration
Register control bit settings of each die are kept identical to maintain consistency when switching between
die.
Block Protection
Each Flash die of the dual die stack will maintain its own Block Protection. Updates to the TBPROT and
BPNV bits of each die must be managed separately. By default, each die is configured to be protected
starting at the top (highest address) of each array, but no address range is protected. It is recommended that
the Block Protection settings of each die are kept identical to maintain consistency when switching between
die.
7. Read Identification (RDID)
The Read Identification (RDID) command outputs the one-byte manufacturer identification, followed by the
two-byte device identification and the bytes for the Common Flash Interface (CFI) tables. Each die of the
FL256P dual die stack will have identical identification data as the FL129P die, with the exception of the CFI
data at byte 27h, as shown in Table 7.1.
Table 7.1 Product Group CFI Device Geometry Definition
Byte
27h
Data
19h
Description
Device Size = 2^N byte
January 30, 2013 S70FL256P_00_05
S70FL256P
11
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| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet S70FL256P.PDF ] | |
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