PDF HMT451U6AFR8C Data sheet ( Hoja de datos )

Número de pieza	HMT451U6AFR8C
Descripción	DDR3 SDRAM
Fabricantes	Hynix Semiconductor
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No Preview Available ! 240pin DDR3 SDRAM Unbuffered DIMM DDR3 SDRAM Unbuffered DIMMs Based on 4Gb A-Die HMT425U6AFR6C HMT451U6AFR8C HMT451U7AFR8C HMT41GU6AFR8C HMT41GU7AFR8C SK hynix reserves the right to change products or specifications without notice. Rev. 1.1 /Jul. 2013 1 Free Datasheet http://www.datasheet4u.com/ 1 page Pin Descriptions Pin Name Description Pin Name Description A0–A15 BA0–BA2 RAS CAS WE S0–S1 CKE0–CKE1 ODT0–ODT1 DQ0–DQ63 CB0–CB7 DQS0–DQS8 DQS0–DQS8 DM0–DM8 CK0–CK1 CK0–CK1 SDRAM address bus SDRAM bank select SDRAM row address strobe SDRAM column address strobe SDRAM write enable DIMM Rank Select Lines SDRAM clock enable lines On-die termination control lines DIMM memory data bus DIMM ECC check bits SDRAM data strobes (positive line of differential pair) SDRAM data strobes (negative line of differential pair) SDRAM data masks/high data strobes (x8-based x72 DIMMs) SDRAM clocks (positive line of differential pair) SDRAM clocks (negative line of differential pair) SCL SDA SA0–SA2 VDD VDDQ* VREFDQ VREFCA VSS VDDSPD NC TEST RESET VTT RSVD - I2C serial bus clock for EEPROM I2C serial bus data line for EEPROM I2C slave address select for EEPROM SDRAM core power supply SDRAM I/O Driver power supply SDRAM I/O reference supply SDRAM command/address reference supply Power supply return (ground) Serial EEPROM positive power supply Spare pins (no connect) Memory bus analysis tools (unused on memory DIMMS) Set DRAMs to Known State SDRAM I/O termination supply Reserved for future use - *The VDD and VDDQ pins are tied common to a single power-plane on these designs Rev. 1.1 / Jul. 2013 5 Free Datasheet http://www.datasheet4u.com/ 5 Page Functional Block Diagram 2GB, 256Mx64 Module(1Rank of x16) S0 DQS0 DQS0 DM0 DQS1 DQS1 DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D0 ZQ DQS4 DQS4 DM4 DQS5 DQS5 DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS D2 ZQ DQS2 DQS2 DM2 DQS3 DQS3 DM3 BA0–BA2 A0–A14 RAS CAS CKE0 WE ODT0 CK0 CK0 RESET DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CSD1 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS ZQ DQS6 DQS6 DM6 DQS7 DQS7 DM7 Serial PD SCL BA0–BA2: SDRAMs D0–D3 A0–A14: SDRAMs D0–D3 RAS: SDRAMs D0–D3 WP A0 A1 A2 SA0 SA1 SA2 CAS: SDRAMs D0–D3 CKE: SDRAMs D0–D3 WE: SDRAMs D0–D3 ODT: SDRAMs D0–D3 CK: SDRAMs D0–D3 CK: SDRAMs D0–D3 RESET:SDRAMs D0-D3 VDDSPD VDD/VDDQ VREFDQ VSS VREFCA DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQS LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS CSD3 UDQS UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 CS ZQ Notes: 1. DQ-to-I/O wiring is shown as recom- mended but may be changed. SDA 2. DQ/DQS/DQS/ODT/DM/CKE/S relation- ships must be maintained as shown. 3. DQ,DM,DQS,DQS resistors;Refer to asso- ciated topology diagram. 4. Refer to the appropriate clock wiring topology under the DIMM wiring details section of this document. SPD 5. The pair CK1 and CK1# is terminated in D0–D3 75ohm but is not used on the module. 6. A15 is not routed on the module. D0–D3 D0–D3 7. For each DRAM, a unique ZQ resistor is connected to ground.The ZQ resistor is 240ohm+-1% D0–D3 8. One SPD exists per module. Rev. 1.1 / Jul. 2013 11 Free Datasheet http://www.datasheet4u.com/ 11 Page

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