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Número de pieza | LAN9303 | |
Descripción | Small Form Factor Three Port 10/100 Managed Ethernet Switch | |
Fabricantes | SMSC | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de LAN9303 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! LAN9303/LAN9303i
Small Form Factor Three
Port 10/100 Managed
Ethernet Switch with Single
MII/RMII/Turbo MII
PRODUCT FEATURES
Datasheet
Highlights
Up to 200Mbps via Turbo MII Interface
High performance, full featured 3 port switch with
VLAN, QoS packet prioritization, Rate Limiting, IGMP
monitoring and management functions
Serial management via I2C or SMI
Unique Virtual PHY feature simplifies software
development by mimicking the multiple switch ports
as a single port PHY
Target Applications
Cable, satellite, and IP set-top boxes
Digital televisions
Digital video recorders
VoIP/Video phone systems
Home gateways
Test/Measurement equipment
Industrial automation systems
Key Benefits
Ethernet Switch Fabric
— 32K buffer RAM
— 512 entry forwarding table
— Port based IEEE 802.1Q VLAN support (16 groups)
– Programmable IEEE 802.1Q tag insertion/removal
— IEEE 802.1D spanning tree protocol support
— 4 separate transmit queues available per port
— Fixed or weighted egress priority servicing
— QoS/CoS Packet prioritization
– Input priority determined by VLAN tag, DA lookup,
TOS, DIFFSERV or port default value
– Programmable Traffic Class map based on input
priority on per port basis
– Remapping of 802.1Q priority field on per port basis
– Programmable rate limiting at the ingress with
coloring and random early discard, per port / priority
– Programmable rate limiting at the egress with leaky
bucket algorithm, per port / priority
— IGMP v1/v2/v3 monitoring for Multicast packet filtering
— Programmable broadcast storm protection with global
% control and enable per port
— Programmable buffer usage limits
— Dynamic queues on internal memory
— Programmable filter by MAC address
Switch Management
— Port mirroring/monitoring/sniffing: ingress and/or egress
traffic on any port or port pair
— Fully compliant statistics (MIB) gathering counters
— Control registers configurable on-the-fly
Ports
— Port 0 - MII MAC, MII PHY, RMII PHY modes
— 2 internal 10/100 PHYs with HP Auto-MDIX support
— 200Mbps Turbo MII (PHY or MAC mode)
— Fully compliant with IEEE 802.3 standards
— 10BASE-T and 100BASE-TX support
— Full and half duplex support
— Full duplex flow control
— Backpressure (forced collision) half duplex flow control
— Automatic flow control based on programmable levels
— Automatic 32-bit CRC generation and checking
— 2K Jumbo packet support
— Programmable interframe gap, flow control pause value
— Full transmit/receive statistics
— Full LED support per port
— Auto-negotiation
— Automatic polarity correction
— Automatic MDI/MDI-X
— Loop-back mode
Serial Management
— I2C (slave) access to all internal registers
— MIIM (MDIO) access to PHY related registers
— SMI (extended MIIM) access to all internal registers
Other Features
— General Purpose Timer
— I2C Serial EEPROM interface
— Programmable GPIOs/LEDs
Single 3.3V power supply
ESD Protection Levels
— ±8kV HBM without External Protection Devices
— ±8kV contact mode (IEC61000-4-2)
— ±15kV air-gap discharge mode (IEC61000-4-2)
Latch-up exceeds ±150mA per EIA/JESD 78
56-pin QFN (8x8 mm) Lead-Free RoHS Compliant
Package
Available in Commercial & Industrial Temp. Ranges
SMSC LAN9303/LAN9303i
DATASHEET
Revision 1.3 (08-27-09)
Free Datasheet http://www.datasheet4u.com/
1 page Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
7.2.2.3
7.2.2.4
7.2.2.5
7.2.2.6
7.2.2.7
7.2.3
NRZI and MLT-3 Decoding ............................................................................................................................................................................. 94
Descrambler and SIPO ................................................................................................................................................................................... 94
5B/4B Decoding .............................................................................................................................................................................................. 94
Receiver Errors ............................................................................................................................................................................................... 94
MII MAC Interface ........................................................................................................................................................................................... 94
10BASE-T Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.3.1
7.2.3.2
7.2.4
MII MAC Interface ........................................................................................................................................................................................... 95
10M TX Driver and PLL .................................................................................................................................................................................. 95
10BASE-T Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
7.2.4.1
7.2.4.2
7.2.4.3
7.2.4.4
7.2.5
Filter and Squelch ........................................................................................................................................................................................... 95
10M RX and PLL............................................................................................................................................................................................. 95
MII MAC Interface ........................................................................................................................................................................................... 96
Jabber Detection............................................................................................................................................................................................. 96
PHY Auto-negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
7.2.5.1
7.2.5.2
7.2.5.3
7.2.5.4
7.2.5.5
7.2.6
PHY Pause Flow Control ................................................................................................................................................................................ 97
Parallel Detection............................................................................................................................................................................................ 98
Restarting Auto-Negotiation............................................................................................................................................................................ 98
Disabling Auto-Negotiation ............................................................................................................................................................................. 98
Half Vs. Full-Duplex ........................................................................................................................................................................................ 98
HP Auto-MDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2.7 MII MAC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2.8 PHY Management Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.8.1 PHY Interrupts .............................................................................................................................................................................................. 100
7.2.9 PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2.9.1 PHY General Power-Down ........................................................................................................................................................................... 101
7.2.9.2 PHY Energy Detect Power-Down ................................................................................................................................................................. 101
7.2.10 PHY Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2.10.1
7.2.10.2
7.2.10.3
7.2.11
PHY Software Reset via RESET_CTL.......................................................................................................................................................... 101
PHY Software Reset via PHY_BASIC_CTRL_x ........................................................................................................................................... 101
PHY Power-Down Reset............................................................................................................................................................................... 101
LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.2.12 Required Ethernet Magnetics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3 Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3.1 Virtual PHY Auto-Negotiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
7.3.1.1
7.3.1.2
7.3.1.3
7.3.2
Parallel Detection.......................................................................................................................................................................................... 103
Disabling Auto-Negotiation ........................................................................................................................................................................... 103
Virtual PHY Pause Flow Control ................................................................................................................................................................... 104
Virtual PHY in MAC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.3.2.1 Full-Duplex Flow Control............................................................................................................................................................................... 104
7.3.3 Virtual PHY Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.3.3.1
7.3.3.2
Virtual PHY Software Reset via RESET_CTL .............................................................................................................................................. 104
Virtual PHY Software Reset via VPHY_BASIC_CTRL ................................................................................................................................. 105
Chapter 8 Serial Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.2 I2C Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
8.3 I2C Master EEPROM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
8.3.1 I2C EEPROM Device Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.3.2 I2C EEPROM Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.3.3 I2C EEPROM Sequential Byte Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.3.4 I2C EEPROM Byte Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
8.3.5 Wait State Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
8.3.6
8.3.6.1
8.3.6.2
8.3.6.3
8.3.6.4
8.3.7
I2C Bus Arbitration and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Bus Busy....................................................................................................................................................................................................... 110
Clock Synchronization .................................................................................................................................................................................. 110
Arbitration...................................................................................................................................................................................................... 111
Timeout Due to Busy or Arbitration............................................................................................................................................................... 111
I2C Master EEPROM Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
8.4 EEPROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.4.1 EEPROM Loader Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
8.4.2 EEPROM Valid Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.4.3 MAC Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.4.4 Soft-Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.4.4.1
8.4.4.2
8.4.4.3
8.4.5
PHY Registers Synchronization.................................................................................................................................................................... 115
Virtual PHY Registers Synchronization......................................................................................................................................................... 116
LED and Manual Flow Control Register Synchronization ............................................................................................................................. 116
Register Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SMSC LAN9303/LAN9303i
5
DATASHEET
Revision 1.3 (08-27-09)
Free Datasheet http://www.datasheet4u.com/
5 Page Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
List of Tables
Table 2.1 Device Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3.1 LAN Port 1 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3.2 LAN Port 2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 3.3 LAN Port 1 & 2 Power and Common Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3.4 Port 0 MII/RMII Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 3.5 GPIO/LED/Configuration Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 3.6 Serial Management/EEPROM Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 3.7 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 3.8 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3.9 Core and I/O Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 3.10 LAN9303/LAN9303i 56-QFN Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 3.11 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 4.1 Reset Sources and Affected Device Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 4.2 Soft-Strap Configuration Strap Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 4.3 Hard-Strap Configuration Strap Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 4.4 PIN/Shared Strap Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 6.1 Switch Fabric Flow Control Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 6.2 Spanning Tree States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 6.3 Typical Ingress Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 6.4 Typical Broadcast Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 6.5 Typical Egress Rate Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 7.1 Default PHY Serial MII Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 7.2 4B/5B Code Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 7.3 PHY Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 8.1 I2C EEPROM Size Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 8.2 EEPROM Contents Format Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 8.3 EEPROM Configuration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 10.1 SMI Frame Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 10.2 MII Management Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 12.1 LED Operation as a Function of LED_FUN[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 13.1 Register Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 13.2 System Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 13.3 SWITCH_MAC_ADDRL, SWITCH_MAC_ADDRH, and EEPROM Byte Ordering . . . . . . . . 162
Table 13.4 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map . . . . . . . . . . . . 164
Table 13.5 Virtual PHY MII Serially Adressable Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 13.6 Emulated Link Partner Pause Flow Control Ability Default Values . . . . . . . . . . . . . . . . . . . . 179
Table 13.7 Emulated Link Partner Default Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 13.8 Port 1 & 2 PHY MII Serially Adressable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 13.9 10BASE-T Full Duplex Advertisement Default Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 13.1010BASE-T Half Duplex Advertisement Bit Default Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 13.11MODE[2:0] Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 13.12Auto-MDIX Enable and Auto-MDIX State Bit Functionality . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 13.13MDIX Strap Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 13.14Indirectly Accessible Switch Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 13.15Metering/Color Table Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 14.1 Supply and Current (10BASE-T Full-Duplex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 14.2 Supply and Current (100BASE-TX Full-Duplex) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 14.3 Supply and Current (Power Management) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
Table 14.4 I/O Buffer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
Table 14.5 100BASE-TX Transceiver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table 14.6 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Table 14.7 nRST Reset Pin Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Table 14.8 Power-On Configuration Strap Latching Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
SMSC LAN9303/LAN9303i
11
DATASHEET
Revision 1.3 (08-27-09)
Free Datasheet http://www.datasheet4u.com/
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet LAN9303.PDF ] |
Número de pieza | Descripción | Fabricantes |
LAN9303 | Small Form Factor Three Port 10/100 Managed Ethernet Switch | SMSC |
LAN9303I | Small Form Factor Three Port 10/100 Managed Ethernet Switch | SMSC |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
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