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PDF ADIS16448 Data sheet ( Hoja de datos )
| Número de pieza | ADIS16448 | |
| Descripción | Ten Degrees of Freedom Inertial Sensor | |
| Fabricantes | Analog Devices | |
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Data Sheet
Compact, Precision
Ten Degrees of Freedom Inertial Sensor
ADIS16448
FEATURES
GENERAL DESCRIPTION
Triaxial digital gyroscope with digital range scaling
±250°/sec, ±500°/sec, ±1000°/sec settings
Axis-to-axis alignment, <0.05°
Triaxial digital accelerometer, ±18 g minimum
Triaxial digital magnetometer, ±1.9 gauss minimum
Digital barometer, 10 mbar to 1200 mbar
Calibrated pressure range: 300 mbar to 1100 mbar
Autonomous operation and data collection
No external configuration commands required
205 ms start-up time
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: −40°C to +70°C
SPI-compatible serial interface
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
Bartlett window FIR length, number of taps
Digital I/O: data ready, alarm indicator, general-purpose
Alarms for condition monitoring
Enable external sample clock input up to 1.1 kHz
Single command self test
Single-supply operation: 3.15 V to 3.45 V
2000 g shock survivability
Operating temperature range: −40°C to +85°C
The ADIS16448 iSensor® device is a complete inertial system
that includes a triaxial gyroscope, a triaxial accelerometer, a
triaxial magnetometer, and pressure sensors. Each sensor in
the ADIS16448 combines industry-leading iMEMS® technology
with signal conditioning that optimizes dynamic performance.
The factory calibration characterizes each sensor for sensitivity,
bias, alignment, and linear acceleration (gyroscope bias). As a
result, each sensor has its own dynamic compensation formulas
that provide accurate sensor measurements.
The ADIS16448 provides a simple, cost-effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation systems.
The SPI and register structures provide a simple interface for
data collection and configuration control.
The ADIS16448 has a compatible pinout for systems that currently
use other Analog Devices, Inc., IMU products (ADIS163xx/
ADIS164xx). The ADIS16448 is packaged in a module that is
approximately 24.1 mm × 37.7 mm × 10.8 mm and has a standard
connector interface.
APPLICATIONS
Platform stabilization and control
Navigation
Robotics
FUNCTIONAL BLOCK DIAGRAM
DIO1 DIO2 DIO3 DIO4/CLKIN RST
VDD
SELF TEST
I/O
ALARMS
POWER
MANAGEMENT
TRIAXIAL
GYRO
TRIAXIAL
ACCEL
TRIAXIAL
MAGN
PRESSURE
TEMP
VDD
CALIBRATION
CONTROLLLER
AND
FILTERS
CLOCK
ADIS16448
OUTPUT
DATA
REGISTERS
USER
CONTROL
REGISTERS
SPI
Figure 1.
GND
CS
SCLK
DIN
DOUT
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Free Datasheet http://www.datasheet4u.com/
1 page  
Data Sheet
ADIS16448
TIMING SPECIFICATIONS
TA = 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Parameter
fSCLK
tSTALL
tREADRATE
tCS
tDAV
tDSU
tDHD
tSCLKR, tSCLKF
tDR, tDF
tSFS
t1
tSTDR
tNV
t3
Description
Serial clock
Stall period between data
Read rate
Chip select to SCLK edge
DOUT valid after SCLK edge
DIN setup time before SCLK rising edge
DIN hold time after SCLK rising edge
SCLK rise/fall times, not shown in Timing Diagrams
DOUT rise/fall times, not shown in Timing Diagrams
CS high after SCLK edge
Input sync positive pulse width
Input sync to data ready valid transition
Data invalid time
Input sync period
Normal Mode
Min1 Typ Max
0.01 2.0
9
40
48.8
100
24.4
48.8
5 12.5
5 12.5
5
25
685
210
910
1 Guaranteed by design and characterization, but not tested in production.
2 When using the burst read mode, the stall period is not applicable.
Min1
0.01
N/A2
Burst Read
Typ Max
1.0
48.8
100
24.4
48.8
5 12.5
5 12.5
5
5
685
210
910
Unit
MHz
μs
μs
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
μs
Timing Diagrams
CS
SCLK
DOUT
DIN
tCS
1
MSB
R/W
23
4
56
tDAV
DB14
tDSU
DB13
DB12
tDHD
DB11
DB10
A6 A5 A4 A3 A2
Figure 2. SPI Timing and Sequence
tREADR ATE
tSTALL
CS
15 16
tSFS
DB2
DB1
LSB
D2 D1 LSB
SCLK
CLOCK
Figure 3. Stall Time and Data Rate
t3
tSTDR
t1
DATA
READY
tNV
Figure 4. Input Clock Timing Diagram
Rev. B | Page 5 of 24
Free Datasheet http://www.datasheet4u.com/
5 Page 
Data Sheet
Burst Read Function
The burst read function provides a way to read all of the data
in one continuous stream of bits (no stall time). As shown in
Figure 13, start this mode by setting DIN = 0x3E00, while
keeping CS low for 12 additional, 16-bit read cycles. These
12 cycles produce the following sequence of output registers
on DOUT: DIAG_STAT, XGYRO_OUT, YGYRO_OUT,
ZGYRO_OUT, XACCL_OUT, YACCL_OUT, ZACCL_OUT,
XMAGN_OUT, YMAGN_OUT, ZMAGN_OUT, BARO_OUT,
and TEMP_OUT.
CS 1
23
13
SCLK
DIN GLOB_CMD
DOUT
DIAG_STAT XGYRO_OUT TEMP_OUT
Figure 13. Burst Read Sequence
SPI Read Test Sequence
Figure 14 provides a test pattern for testing the SPI communica-
tion. In this pattern, write 0x5600 to the DIN line in a repeating
pattern and raise chip select for at least 9 μs between each 16-bit
sequence. Starting with the second 16-bit sequence, DOUT
produces the contents of the PROD_ID (see Table 28) register,
0x4040.
CS
SCLK
DIN DIN = 0101 0110 0000 0000 = 0x5600
DOUT
DOUT = 0100 0000 0100 0000 = 0x4040 = 16,448
Figure 14. SPI Test Read Pattern DIN = 0x5600, DOUT = 0x4040
ADIS16448
DEVICE CONFIGURATION
The control registers in Table 6 provide users with a variety of
configuration options. The SPI provides access to these registers,
one byte at a time, using the bit assignments in Figure 12. Each
register has 16 bits, where Bits[7:0] represent the lower address,
and Bits[15:8] represent the upper address. Figure 15 provides
an example of writing 0x04 to Address 0x36 (SMPL_PRD[15:8],
using DIN = 0xB704. This example reduces the sample rate by a
factor of eight (see Table 34).
CS
SCLK
DIN
DIN = 1011 0111 0000 0100 = 0xB704, WRITES 0x04 TO ADDRESS 0x37.
Figure 15. Example SPI Write Sequence
Dual Memory Structure
Writing configuration data to a control register updates its
SRAM contents, which are volatile. After optimizing each
relevant control register setting in a system, set GLOB_CMD[3]
= 1 (DIN = 0xBE08) to backup these settings in nonvolatile
flash memory. The flash backup process requires a valid power
supply level for the entire process time, 75 ms. Table 6 provides
a user register memory map that includes a flash backup
column. A yes in this column indicates that a register has a
mirror location in flash and, when backed up properly, it
automatically restores itself during startup or after a reset.
Figure 16 provides a diagram of the dual memory structure
used to manage operation and store critical user settings.
NONVOLATILE
FLASH MEMORY
(NO SPI ACCESS)
MANUAL
FLASH
BACKUP
START-UP
RESET
VOLATILE
SRAM
SPI ACCESS
Figure 16. SRAM and Flash Memory Diagram
Rev. B | Page 11 of 24
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11 Page | ||
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