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PDF 25A512 Data sheet ( Hoja de datos )

Número de pieza 25A512
Descripción 512 Kbit SPI Bus Serial EEPROM
Fabricantes Microchip Technology 
Logotipo Microchip Technology Logotipo



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25A512
512 Kbit SPI Bus Serial EEPROM
Device Selection Table
Part Number
25A512
VCC Range
1.7-3.0V
Page Size
128 Byte
Temp. Ranges
I
Packages
SN, ST
Features:
• 10 MHz max. Clock Speed
• Byte and Page-level Write Operations
- 128-byte page
- 5 ms max.
- No page or sector erase required
• Low-Power CMOS Technology
- Max. Write Current: 5 mA at 3.0V, 10 MHz
- Read Current: 10 mA at 3.0V, 10 MHz
- Standby Current: 1A at 2.5V (Deep power-
down)
• Electronic Signature for Device ID
• Self-Timed Erase and Write cycles
- Page Erase (5 ms, typical)
- Sector Erase (10 ms/sector, typical)
- Bulk Erase (10 ms, typical)
• Sector Write Protection (16K byte/sector)
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability
- Endurance: 1 Million erase/write cycles
- Data Retention: >200 years
- ESD Protection: 4000V
• Temperature Ranges Supported;
- Industrial (I): -40°C to +85°C
• Pb-free and RoHS Compliant
Pin Function Table
Name
Function
CS
SO
WP
VSS
SI
SCK
HOLD
VCC
Chip Select Input
Serial Data Output
Write-Protect
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
Description:
The Microchip Technology Inc. 25A512 is a 512 Kbit
serial EEPROM memory with byte-level and page-level
serial EEPROM functions. It also features Page, Sector
and Chip erase functions typically associated with
Flash-based products. These functions are not required
for byte or page write operations. The memory is
accessed via a simple Serial Peripheral Interface (SPI)
compatible serial bus. The bus signals required are a
clock input (SCK) plus separate data in (SI) and data
out (SO) lines. Access to the device is controlled by a
Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25A512 is available in standard packages includ-
ing 8-lead SOIC and TSSOP packages. All packages
are Pb-free and RoHS compliant.
Package Types (not to scale)
SOIC/TSSOP
(SN, ST)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
2010-2011 Microchip Technology Inc.
Preliminary
DS22237C-page 1
Free Datasheet http://www.datasheet4u.com/

1 page




25A512 pdf
25A512
TABLE 1-3: AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
CL = 30 pF
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
FIGURE 1-1: HOLD TIMING
CS
16 17
SCK
16 17
18 High-Impedance 19
SO n + 1 n
n
SI n + 1 n
Don’t Care
5
n
HOLD
16 17
16 17
18
n-1
n-1
High-Impedance 19
n-2
Don’t Care
n-2
FIGURE 1-2: SERIAL INPUT TIMING
CS
2
Mode 1,1
SCK Mode 0,0
5
6
SI MSB in
SO
7
High-Impedance
8
4
12
11
3
LSB in
2010-2011 Microchip Technology Inc.
Preliminary
DS22237C-page 5
Free Datasheet http://www.datasheet4u.com/

5 Page





25A512 arduino
25A512
2.3 Write Enable (WREN) and Write
Disable (WRDI)
The 25A512 contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up/BOR
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
PE instruction successfully executed
SE instruction successfully executed
CE instruction successfully executed
FIGURE 2-4:
WRITE ENABLE SEQUENCE (WREN)
CS
SCK
01234567
SI 0 0 0 0 0 1 1 0
High-Impedance
SO
FIGURE 2-5:
WRITE DISABLE SEQUENCE (WRDI)
CS
SCK
01234567
SI 0 0 0 0 0 1 10 0
High-Impedance
SO
2010-2011 Microchip Technology Inc.
Preliminary
DS22237C-page 11
Free Datasheet http://www.datasheet4u.com/

11 Page







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