ADAU1978 Datasheet PDF - Analog Devices
| Part Number | ADAU1978 | |
| Description | Quad Analog-to-Digital Converter | |
| Manufacturers | Analog Devices | |
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Data Sheet
Quad Analog-to-Digital Converter (ADC)
ADAU1978
FEATURES
Four 2 V rms differential inputs
On-chip phase-locked loop (PLL) for master clock
Low electromagnetic interference (EMI) design
106 dB analog-to-digital converter (ADC) dynamic range
Total harmonic distortion + noise (THD + N): −95 dB
Selectable digital high-pass filter
24-bit stereo ADC with 8 kHz to 192 kHz sample rates
Digital volume control with autoramp function
I2C/SPI controllable for flexibility
Software-controllable clickless mute
Software power-down
Right justified, left justified, I2S, and TDM modes
Master and slave operation modes
40-lead LFCSP package
Qualified for automotive applications
APPLICATIONS
Automotive audio systems
Active noise cancellation systems
GENERAL DESCRIPTION
The ADAU1978 incorporates four high performance, analog-to-
digital converters (ADCs) with 2 V rms capable ac-coupled inputs.
The ADCs use a multibit sigma-delta (Σ-Δ) architecture with
continuous time front end for low EMI. An I2C/serial peripheral
interface (SPI) control port is included that allows a microcontroller
to adjust volume and many other parameters. The ADAU1978
uses only a single 3.3 V supply. The part internally generates the
required digital DVDD supply. The low power architecture
reduces the power consumption. The ADAU1978 is available in
a 40-lead LFCSP package. The on-chip PLL can derive the master
clock from an external clock input or frame clock (sample rate
clock). When fed with the frame clock, it eliminates the need
for a separate high frequency master clock in the system.
Note that throughout this data sheet, multifunction pins, such
as SCL/CCLK, are referred to either by the entire pin name or
by a single function of the pin, for example, CCLK, when only
that function is relevant.
FUNCTIONAL BLOCK DIAGRAM
AIN1P
AIN1N
AIN2P
AIN2N
AIN3P
AIN3N
AIN4P
AIN4N
ADAU1978
3.3V TO 1.8V
REGULATOR
ADC
ADC
ADC
ADC
AGND1 AGND3
AVDD2
BG
REF
PLL
AGND2
AGND2
I2C/SPI
CONTROL
DVDD
IOVDD
LRCLK
BCLK
SDATAOUT1
SDATAOUT2
SCL/CCLK
SDA/COUT
ADDR1/CIN
ADDR0/CLATCH
PD/RST
Figure 1.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700
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Technical Support
www.analog.com
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Data Sheet
ADAU1978
TIMING SPECIFICATIONS
Table 5.
Parameter
INPUT MASTER CLOCK (MCLK)
Duty Cycle
fMCLKIN
RESET
Reset Pulse
PLL
Lock Time
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCH
tDS
tDH
tSCR
tSCF
tSDR
tSDF
tBFT
tSUSTO
SPI PORT
fCCLK
tCCPH
tCCPL
tCDS
tCDH
tCLS
tCLH
tCLPH
tCOE
tCOD
tCOTS
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tABDD
Limit at
Min Max Unit Description
40 60
See Table 9
% MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS
MHz MCLKIN frequency, PLL in MCLK mode
15 ns RST low
10
400
0.6
1.3
0.6
0.6
100
0
300
300
300
300
1.3
0.6
10
35
35
10
10
10
40
10
30
30
30
10
10
10
5
18
ms
See Figure 4
kHz SCL frequency
µs SCL high
µs SCL low
µs Setup time; relevant for repeated start condition
µs Hold time; after this period of time, the first clock pulse is generated
ns Data setup time
Data hold time
ns SCL rise time
ns SCL fall time
ns SDA rise time
ns SDA fall time
µs Bus-free time; time between stop and start
µs Setup time for stop condition
see Figure 3
MHz CCLK frequency
ns CCLK high
ns CCLK low
ns CIN setup to CCLK rising
ns CIN hold from CCLK rising
ns CLATCH setup to CCLK rising
ns CLATCH hold from CCLK rising
ns CLATCH high
ns COUT enable from CLATCH falling
ns COUT delay from CCLK falling
ns COUT tristate from CLATCH rising
see Figure 2
ns BCLK high, slave mode
ns BCLK low, slave mode
ns LRCLK setup to BCLK rising, slave mode
ns LRCLK hold from BCLK rising, slave mode
ns SDATAOUTx delay from BCLK falling
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